公开(公告)号：US11107731B1

公开(公告)日：2021-08-31

申请号：US16834725

申请日：2020-03-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Chih-Chao Yang ,  Carl Radens ,  Juntao Li ,  Kangguo Cheng

IPC: H01L21/768 ,  H01L21/3213 ,  H01L23/522

Abstract: A method for fabricating a semiconductor device includes forming conductive material on a first metallization level including at least one via disposed on at least one conductive line, subtractively patterning the conductive material to form at least one conductive layer corresponding to at least one conductive line of a second metallization level misaligned with the at least one via of the first metallization level, and at least one cavity within the at least one via forming at least one damaged via resulting from the misalignment, and filling the at least one cavity with conductive liner material to form a filled cavity to repair the at least one damaged via.

公开(公告)号：US20210265166A1

公开(公告)日：2021-08-26

申请号：US16795718

申请日：2020-02-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Daniel James Dechene ,  Somnath Ghosh ,  Hsueh-Chung Chen ,  Carl Radens ,  Lawrence A. Clevenger

IPC: H01L21/033

Abstract: A method is presented for employing double-patterning to reduce via-to-via spacing. The method includes forming a mandrel layer over a substrate, forming sacrificial hardmask layers over the mandrel layer defining a litho stack, creating a pattern in the litho stack, the pattern having a narrow section connecting two wider sections to define a substantially hour-glass shape, depositing a spacer assuming a shape of the pattern, and etching the litho stack to expose the mandrel layer and metal lines, wherein the metals lines define sharp distal ends reducing a distance between the metal lines.

公开(公告)号：US11081172B1

公开(公告)日：2021-08-03

申请号：US16838157

申请日：2020-04-02

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Carl Radens ,  Ruilong Xie ,  Juntao Li

IPC: G11C11/408 ,  G11C11/4094 ,  G11C11/56 ,  G06F21/71

Abstract: A method is presented for forming an on-chip security key. The method includes electrically connecting a pair of phase change memory (PCM) elements in series, electrically connecting a programming transistor to the pair of PCM elements, electrically connecting an input of an inverter to a common node of the pair of PCM elements, setting the PCM elements to a low resistance state (LRS) in an initialization stage, applying a RESET pulse to generate a security bit and to cause one of the PCM elements to change to a high resistance state (HRS), and generating a logic “1” or “0” at the output of the inverter.

公开(公告)号：US10985063B2

公开(公告)日：2021-04-20

申请号：US16542595

申请日：2019-08-16

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Lawrence A. Clevenger ,  Carl Radens ,  Junli Wang ,  John H. Zhang

IPC: H01L21/70 ,  H01L21/768 ,  H01L27/092 ,  H01L21/8238

Abstract: A first TS is coupled to first S/D over first fin, second TS coupled to second S/D over first fin, third TS coupled to third S/D over second fin, fourth TS coupled to fourth S/D over second fin, gate metal over first and second fins, and gate cap over gate metal. First TS cap is on first TS, second TS cap on second TS, third TS cap on third TS, and fourth TS cap on fourth TS. ILD is formed on top of gate cap and first through fourth TS caps. First opening is through ILD and second TS cap such that part of gate metal is exposed, after removing part of gate cap. Second opening is through ILD to expose another part of gate metal. Combined gate metal contact and local metal connection is formed in first opening and individual gate metal contact is formed in second opening.

公开(公告)号：US10734289B2

公开(公告)日：2020-08-04

申请号：US16539294

申请日：2019-08-13

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Junli Wang ,  Lawrence A. Clevenger ,  Carl Radens ,  John H. Zhang

IPC: H01L21/336 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/762 ,  H01L29/66 ,  H01L27/088 ,  H01L27/092 ,  H01L21/84 ,  H01L21/8234

Abstract: A semiconductor device is formed to include a fin structure, a first trench at a first lateral end of the fin, a second trench at a second lateral end of the fin, and a filler filled on a first traverse side of the fin and a second traverse side of the fin. The filler is contained between the first trench and the second trench, and oxidized in-place to cause a stress to be exerted on the first and second traverse sides of the fin, the stress causing the fin to exhibit a tensile strain in a lateral running direction of the fin.

公开(公告)号：US20200027787A1

公开(公告)日：2020-01-23

申请号：US16542595

申请日：2019-08-16

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Lawrence A. Clevenger ,  Carl Radens ,  Junli Wang ,  John H. Zhang

IPC: H01L21/768 ,  H01L21/8238 ,  H01L27/092

Abstract: A first TS is coupled to first S/D over first fin, second TS coupled to second S/D over first fin, third TS coupled to third S/D over second fin, fourth TS coupled to fourth S/D over second fin, gate metal over first and second fins, and gate cap over gate metal. First TS cap is on first TS, second TS cap on second TS, third TS cap on third TS, and fourth TS cap on fourth TS. ILD is formed on top of gate cap and first through fourth TS caps. First opening is through ILD and second TS cap such that part of gate metal is exposed, after removing part of gate cap. Second opening is through ILD to expose another part of gate metal. Combined gate metal contact and local metal connection is formed in first opening and individual gate metal contact is formed in second opening.

公开(公告)号：US10516064B1

公开(公告)日：2019-12-24

申请号：US16103283

申请日：2018-08-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Lawrence A. Clevenger ,  Carl Radens ,  Junli Wang ,  John H. Zhang

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L27/088 ,  H01L29/66 ,  H01L29/40 ,  H01L29/417

Abstract: A technique relates to a semiconductor device. A first stack includes a first plurality of nanowires respectively coupled to first source and drain regions, and a second stack includes a second plurality of nanowires respectively coupled to second source and drain regions. First source and drain contacts couple to a first predefined number of the first plurality of nanowires. Second source and drain contacts to couple to a second predefined number of the second plurality of nanowires, wherein the first predefined number is different from the second predefined number.

公开(公告)号：US10325778B2

公开(公告)日：2019-06-18

申请号：US15801039

申请日：2017-11-01

Applicant: International Business Machines Corporation

Inventor： Lawrence A. Clevenger ,  John H. Zhang ,  Carl Radens

IPC: H01L21/302 ,  H01L21/308 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768

Abstract: A chemical material is deposited on a surface of a substrate. A mandrel composition is deposited on a surface of the chemical material. A mandrel hard mask pattern is deposited on a surface of the mandrel composition. The mandrel composition is etched. The mandrel hard mask pattern is removed. A plurality of spacer materials are deposited sequentially onto a surface of the chemical material and a surface of the mandrel composition. A portion of each of the plurality of spacer materials are removed sequentially. A remainder of the mandrel composition is removed. The substrate is etched. The chemical material and at least one of the spacer materials of the plurality of spacer materials are removed.

公开(公告)号：US20190067023A1

公开(公告)日：2019-02-28

申请号：US15690540

申请日：2017-08-30

Applicant: International Business Machines Corporation

Inventor： Lawrence A. Clevenger ,  John H. Zhang ,  Carl Radens

IPC: H01L21/308

Abstract: A chemical material is deposited on a surface of a substrate. A mandrel composition is deposited on a surface of the chemical material. A mandrel hard mask pattern is deposited on a surface of the mandrel composition. The mandrel composition is etched. The mandrel hard mask pattern is removed. A plurality of spacer materials are deposited sequentially onto a surface of the chemical material and a surface of the mandrel composition. A portion of each of the plurality of spacer materials are removed sequentially. A remainder of the mandrel composition is removed. The substrate is etched. The chemical material and at least one of the spacer materials of the plurality of spacer materials are removed.

公开(公告)号：US20160293589A1

公开(公告)日：2016-10-06

申请号：US15175738

申请日：2016-06-07

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： John H. Zhang ,  Lawrence A. Clevenger ,  Carl Radens ,  Yiheng Xu ,  Edem Wornyo

IPC: H01L27/01 ,  H01L23/525

CPC classification number: H01L27/016 ,  H01L21/31053 ,  H01L21/3212 ,  H01L23/5223 ,  H01L23/5228 ,  H01L23/5252 ,  H01L23/5256 ,  H01L28/20 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A sequence of semiconductor processing steps permits formation of both vertical and horizontal nanometer-scale serpentine resistors and parallel plate capacitors within a common structure. The method takes advantage of a CMP process non-uniformity in which the CMP polish rate of an insulating material varies according to a certain underlying topography. By establishing such topography underneath a layer of the insulating material, different film thicknesses of the insulator can be created in different areas by leveraging differential polish rates, thereby avoiding the use of a lithography mask. In one embodiment, a plurality of resistors and capacitors can be formed as a compact integrated structure within a common dielectric block, using a process that requires only two mask layers. The resistors and capacitors thus formed as a set of integrated circuit elements are suitable for use as microelectronic fuses and antifuses, respectively, to protect underlying microelectronic circuits.

Abstract translation: 半导体处理步骤的顺序允许在公共结构内形成垂直和水平的纳米级蛇形电阻器和平行板电容器。 该方法利用CMP工艺不均匀性，其中绝缘材料的CMP抛光速率根据某些底层的形貌而变化。 通过在绝缘材料层之下建立这样的形貌，可以通过利用差分抛光速率在不同的区域产生绝缘体的不同膜厚度，从而避免使用光刻掩模。 在一个实施例中，使用仅需要两个掩模层的工艺，可以在公共介电块内形成多个电阻器和电容器作为紧凑的集成结构。 这样形成为一组集成电路元件的电阻器和电容器分别适合用作微电子熔丝和反熔丝，以保护下面的微电子电路。