公开(公告)号：US20160293695A1

公开(公告)日：2016-10-06

申请号：US14391889

申请日：2014-08-15

申请人： INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

发明人： Jing Xu ,  Jiang Yan ,  Bangming Chen ,  Hongli Wang ,  Bo Tang ,  Zhaoyun Tang ,  Yefeng Xu ,  Chunlong Li ,  Mengmeng Yang

IPC分类号： H01L29/06 ,  H01L21/02 ,  H01L29/78 ,  H01L21/762 ,  H01L21/306 ,  H01L29/161 ,  H01L21/764

CPC分类号： H01L29/0649 ,  H01L21/30604 ,  H01L21/762 ,  H01L21/764 ,  H01L29/0653 ,  H01L29/161 ,  H01L29/66568 ,  H01L29/78

摘要： The present disclosure provides a semiconductor device, comprising: a substrate having a first semiconductor material; a second semiconductor layer on the substrate; a third semiconductor layer on the second semiconductor layer and being a device formation region; an isolation structure on both sides of the third semiconductor layer and on the substrate; and an hollow cavity below the source and drain regions of the third semiconductor layer and between the isolation structure and the ends of the second semiconductor layer. Such a device structure of the present disclosure incorporate the respective advantages of the bulk silicon device and the SOI device, and has characteristics of lower cost, smaller leakage current, lower power consumption, fast speed, simple process and high integration level. Meanwhile, the floating body effect and the spontaneous heating effect are eliminated as compared with the SOI device. Furthermore, the lower dielectric constant in the hollow cavity results in that it may withstand a higher voltage.

摘要翻译： 本公开提供一种半导体器件，包括：具有第一半导体材料的衬底; 在所述基板上的第二半导体层; 第二半导体层上的第三半导体层，并且是器件形成区域; 在第三半导体层的两侧和基板上的隔离结构; 以及在第三半导体层的源极和漏极区之下以及隔离结构和第二半导体层的端部之间的中空腔。 本公开的这种器件结构体现了本体硅器件和SOI器件的各自优点，具有成本更低，漏电流更小，功耗更低，速度快，工艺简单，集成度高的特点。 同时，与SOI器件相比，浮体效应和自发加热效应被消除。 此外，中空腔中的较低介电常数导致其可承受更高的电压。

公开(公告)号：US09461068B2

公开(公告)日：2016-10-04

申请号：US14761262

申请日：2013-03-11

申请人： INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

发明人： Huilong Zhu

IPC分类号： H01L29/78 ,  H01L27/12 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/165 ,  H01L21/84

CPC分类号： H01L27/1211 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/42364 ,  H01L29/66484 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7855

摘要： Semiconductor arrangements and methods for manufacturing the same are provided. In one embodiment, the arrangement may include: a semiconductor on insulator (SOI) substrate, comprising a base substrate, a buried dielectric layer, and a SOI layer; a back gate formed on the SOI substrate and passing through the buried dielectric layer to be in electric contact with the base substrate; fins formed from the SOI layer on opposite sides of the back gate; and back gate dielectric layers interposed between the back gate and the respective fins.

摘要翻译： 提供了半导体装置及其制造方法。 在一个实施例中，该布置可以包括：绝缘体上半导体（SOI）衬底，包括基底衬底，埋入介质层和SOI层; 形成在SOI衬底上并通过掩埋电介质层以与基底电接触的背栅; 在后门的相对侧由SOI层形成的翅片; 以及介于后栅极和相应散热片之间的背栅电介质层。

公开(公告)号：US20160276467A1

公开(公告)日：2016-09-22

申请号：US14905465

申请日：2013-10-22

申请人： INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

发明人： Yunfei Liu ,  Haizhou Yin ,  Keke Zhang

IPC分类号： H01L29/66 ,  H01L29/49 ,  H01L29/06

CPC分类号： H01L29/66795 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/7853

摘要： A method of manufacturing a FinFET device is provided, comprising: a. providing a substrate (100); b. forming a fin (200) on the substrate; c. forming an shallow trench isolation structure (300) on the substrate; d. forming an sacrificial gate stack on the isolation structure, wherein the sacrificial gate stack intersects the fin; e. forming source/drain doping regions by ion implantation into the fin; f. depositing an interlayer dielectric layer (400) on the substrate; g. removing the sacrificial gate stack to form a sacrificial gate vacancy; h. forming an doped region (201) under the sacrificial gate vacancy; i. etching the shallow trench isolation structure (300) under the sacrificial gate vacancy until the top surface of the shallow trench isolation structure (300) levels with the bottom surface of the source/drain doping regions; j. forming a new gate stack in the sacrificial gate vacancy. Some advantages of the current invention may be, harmful effects produced in the source/drain regions by the triangle fin structure are eliminated, the device performance is improved, and the complexity of the process is reduce.

摘要翻译： 提供一种制造FinFET器件的方法，包括：a。 提供衬底（100）; b。 在所述基板上形成翅片（200）; C。 在衬底上形成浅沟槽隔离结构（300）; d。 在所述隔离结构上形成牺牲栅极堆叠，其中所述牺牲栅极堆叠与所述鳍片相交; e。 通过离子注入形成源极/漏极掺杂区域; F。 在衬底上沉积层间电介质层（400）; G。 去除牺牲栅极堆叠以形成牺牲栅极空位; H。 在牺牲栅极空位下形成掺杂区域（201）; 一世。 在牺牲栅极空位下蚀刻浅沟槽隔离结构（300），直到浅沟槽隔离结构（300）的顶表面与源极/漏极掺杂区域的底表面一致; j。 在牺牲栅极空位中形成新的栅极堆叠。 本发明的一些优点可以是消除由三角鳍结构在源极/漏极区域产生的有害影响，提高了器件性能，并且降低了工艺的复杂性。

公开(公告)号：US20160163592A1

公开(公告)日：2016-06-09

申请号：US14943706

申请日：2015-11-17

申请人： Institute of Microelectronics, Chinese Academy of Sciences

发明人： Huicai ZHONG ,  Chao ZHAO ,  Huilong ZHU

IPC分类号： H01L21/768

CPC分类号： H01L21/486 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/49827

摘要： In a method for manufacturing a semiconductor, a Through Silicon Via (TSV) template wafer and production wafers form a sandwich structure, in which the TSV template wafer has TSV structures uniformly distributed therein, for providing electrical connection between the production wafers to form 3D interconnection. The TSV template wafer is obtained by thinning a semiconductor wafer, which facilitates reducing the difficulty in etching and filling. Connection parts are provided on the TSV template wafer, for convenience of interconnection between the overlying and underlying production wafers, which facilitates reducing the difficulty in alignment and improving the convenience of design of electrical connection for 3D devices.

摘要翻译： 在制造半导体的方法中，透明硅（TSV）模板晶片和生产晶片形成夹层结构，其中TSV模板晶片具有均匀分布在其中的TSV结构，用于在生产晶片之间提供电连接以形成3D互连 。 通过减薄半导体晶片获得TSV模板晶片，这有助于降低蚀刻和填充的难度。 在TSV模板晶片上提供连接部件，以方便上层和下面的生产晶圆之间的互连，这有助于降低对准难度，并提高3D设备电气连接设计的便利性。

公开(公告)号：US20160123943A1

公开(公告)日：2016-05-05

申请号：US14895915

申请日：2013-06-05

申请人： INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

发明人： Dongmei LI ,  Hao ZHANG ,  Shengfa LIANG ,  Qing LUO ,  Xiaojing LI ,  Changqing XIE ,  Ming LIU

IPC分类号： G01N33/00

CPC分类号： G01N33/0034 ,  G06N3/084

摘要： A gas recognition method based on a compressive sensing theory. The method comprises: collecting compressed data in an under-sampling manner; performing a reconstruction on the collected compressed data to obtain reconstructed data; training a back-propagation neural network by using the reconstructed data and storing the trained back-propagation neural network; inputting data under test into the trained back-propagation neural network, such that the trained back-propagation neural network performs a recognition on the data under test to realize qualitative recognition of gas. The method solves the problem in transmission and storage of large amount of data and the problem of imprecise recognition in current gas detection, and achieves the object that a precise qualitative recognition is achieved by using a reduced amount of data.

摘要翻译： 一种基于压缩感知理论的气体识别方法。 该方法包括：以低采样方式收集压缩数据; 对所收集的压缩数据进行重构以获得重构数据; 通过使用重构数据训练反向传播神经网络，并存储经过训练的反向传播神经网络; 将被测数据输入到经过训练的反向传播神经网络中，使得经过训练的反向传播神经网络对被测数据进行识别，以实现气体的定性识别。 该方法解决了大量数据的传输和存储问题，以及当前气体检测中不精确识别的问题，达到了通过减少数据量实现精确定性识别的对象。

公开(公告)号：US20160087063A1

公开(公告)日：2016-03-24

申请号：US14696616

申请日：2015-04-27

申请人： INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

发明人： Huaxiang Yin ,  Yongkui Zhang ,  Zhiguo Zhao ,  Zhiyong Lu ,  Huilong Zhu

IPC分类号： H01L29/49 ,  H01L29/66 ,  H01L29/10 ,  H01L21/265 ,  H01L27/088 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/324

CPC分类号： H01L29/4916 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L27/0886 ,  H01L29/1083 ,  H01L29/66492 ,  H01L29/66537 ,  H01L29/66545

摘要： A semiconductor device is provided that has a plurality of Fin structures extending on a substrate along a first direction; a gate stack structure extending on the substrate along a second direction and across the plurality of Fin structures, wherein the gate stack structure comprises a gate conductive layer and a gate insulating layer, and the gate conductive layer is formed by a doped poly-semiconductor; trench regions in the plurality of Fin structures and beneath the gate stack structure; and source/drain regions on the plurality of Fin structures and at both sides of the gate stack structure along the first direction. A method of manufacturing a semiconductor device is also provided.

摘要翻译： 提供一种半导体器件，其具有沿着第一方向在衬底上延伸的多个鳍结构; 栅极堆叠结构，其沿着第二方向延伸并跨越所述多个Fin结构，其中所述栅极堆叠结构包括栅极导电层和栅极绝缘层，并且所述栅极导电层由掺杂的多晶半导体形成; 多个鳍结构中的沟槽区域和栅极堆叠结构下方的沟槽区域; 以及多个Fin结构上的源极/漏极区域以及沿着第一方向的栅极堆叠结构的两侧。 还提供了一种制造半导体器件的方法。

公开(公告)号：US20160079969A1

公开(公告)日：2016-03-17

申请号：US14888335

申请日：2013-07-15

申请人： INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

发明人： Dongmei LI ,  Qing LUO ,  Shengfa LIANG ,  Hongzhang YANG ,  Xiaojing LI ,  Hao ZHANG ,  Changqing XIE ,  Ming LIU

IPC分类号： H03K4/08

CPC分类号： H03K4/08 ,  A61B5/00 ,  H03K3/84 ,  H03K4/50

摘要： A sampler adapted to a one-dimension slow-varying signal, including: a signal preprocessing unit configured to preprocess an input signal; a slope-controllable sawtooth wave signal generating unit configured to generate a slope-controllable sawtooth wave signal and perform zero-resetting; a signal comparing unit configured to compare the preprocessed input signal from the signal preprocessing unit with the sawtooth wave signal and to output a pulse signal to the generating unit and a signal outputting unit when the preprocessed input signal is equal to the sawtooth wave signal; a counting unit configured to count a number of clock signals while the sawtooth wave signal generating unit is generating the sawtooth wave signal and to transmit the counted number to the signal outputting unit; the signal outputting unit configured to, upon receipt of the pulse signal output from the signal comparing unit, output the number counted by the counting unit at the moment.

摘要翻译： 一种适于一维慢变信号的采样器，包括：信号预处理单元，被配置为预处理输入信号; 坡度可控锯齿波信号产生单元，其被配置为产生斜率可控锯齿波信号并执行零重置; 信号比较单元，被配置为将来自信号预处理单元的预处理输入信号与锯齿波信号进行比较，并且当预处理输入信号等于锯齿波信号时，向生成单元输出脉冲信号和信号输出单元; 计数单元，被配置为在锯齿波信号生成单元产生锯齿波信号的同时对多个时钟信号进行计数，并将计数的数量发送到信号输出单元; 所述信号输出单元被配置为在接收到从所述信号比较单元输出的脉冲信号时，输出由所述计数单元计数的数量。

公开(公告)号：US20150340464A1

公开(公告)日：2015-11-26

申请号：US14814003

申请日：2015-07-30

申请人： Institute of Microelectronics, Chinese Academy of Sciences

发明人： Zhaoyun TANG ,  Jiang YAN

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L29/06 ,  H01L21/265 ,  H01L29/78 ,  H01L29/423

CPC分类号： H01L29/66621 ,  H01L21/02233 ,  H01L21/02255 ,  H01L21/26513 ,  H01L21/308 ,  H01L29/0649 ,  H01L29/4236 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/78654

摘要： A semiconductor device manufacturing method includes forming a gate opening in a semiconductor layer; forming a sacrificial gate in the gate opening; forming a source region and a drain region in the semiconductor layer in proximity to the gate opening; removing the sacrificial gate; and forming a gate stack comprising a replacement gate dielectric layer and a replacement gate conductor layer in the gate opening, wherein the gate opening is configured to define a thickness of a portion of the semiconductor layer for a channel region. Channel control in semiconductor devices formed according to the above method can be effectively improved.

摘要翻译： 半导体器件制造方法包括在半导体层中形成栅极开口; 在闸门开口形成牺牲栅; 在所述栅极开口附近的所述半导体层中形成源极区域和漏极区域; 去除牺牲门; 以及在所述栅极开口中形成包括替换栅极介电层和替换栅极导体层的栅极堆叠，其中所述栅极开口被配置为限定所述半导体层对于沟道区域的一部分的厚度。 可以有效地提高根据上述方法形成的半导体器件中的沟道控制。

公开(公告)号：US20150340456A1

公开(公告)日：2015-11-26

申请号：US14412173

申请日：2012-07-19

申请人： INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

发明人： Haizhou YIN ,  Huilong ZHU ,  Keke ZHANG

IPC分类号： H01L29/423 ,  H01L29/78 ,  H01L21/3105 ,  H01L21/28 ,  H01L29/66

CPC分类号： H01L21/28114 ,  H01L21/28088 ,  H01L21/31051 ,  H01L29/41783 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/78 ,  H01L29/7834

摘要： A method for manufacturing a semiconductor device is disclosed. The method comprises: forming a T-shape dummy gate structure on the substrate; removing the T-shape dummy gate structure and retaining a T-shape gate trench; forming a T-shape metal gate structure by filling a metal layer in the T-shape gate trench. According to the semiconductor device manufacturing method disclosed in the present application, the overhang phenomenon and the formation of voids are avoided in the subsequent metal gate filling process by forming a T-shape dummy gate and a T-shape gate trench, and the device performance is improved.

摘要翻译： 公开了一种制造半导体器件的方法。 该方法包括：在衬底上形成T形虚拟栅极结构; 去除T形虚拟栅极结构并保持T形栅极沟槽; 通过在T形栅极沟槽中填充金属层来形成T形金属栅极结构。 根据本申请中公开的半导体器件制造方法，通过形成T形虚拟栅极和T形栅极沟槽，在随后的金属栅极填充处理中避免了突出现象和空隙的形成，并且器件性能 改进了

公开(公告)号：US20150340290A1

公开(公告)日：2015-11-26

申请号：US14441122

申请日：2012-11-19

申请人： INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

发明人： Huilong ZHU

IPC分类号： H01L21/8234 ,  H01L29/06 ,  H01L29/10 ,  H01L27/088 ,  H01L29/165

CPC分类号： H01L21/823481 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/00 ,  H01L29/0649 ,  H01L29/1029 ,  H01L29/165 ,  H01L29/66545

摘要： A semiconductor device and a method for manufacturing the same. An example method may include: forming a first semiconductor layer and a second semiconductor layer sequentially on a substrate; patterning the second and first semiconductor layers to form an initial fin; forming an isolation layer on the substrate, wherein the isolation layer exposes partially the first semiconductor layer, and thus defines a fin above the isolation layer; and forming a gate stack intersecting the fin on the isolation layer, wherein the first semiconductor layer comprises a compound semiconductor, with at least one component whose concentration has a graded distribution in a stack direction of the first and second semiconductor layers.

摘要翻译： 半导体器件及其制造方法。 示例性方法可以包括：在衬底上顺序地形成第一半导体层和第二半导体层; 图案化第二和第一半导体层以形成初始鳍; 在所述衬底上形成隔离层，其中所述隔离层部分地暴露所述第一半导体层，从而限定所述隔离层上方的鳍; 以及在所述隔离层上形成与所述散热片相交的栅极堆叠，其中所述第一半导体层包含化合物半导体，其中所述至少一种组分的浓度在所述第一和第二半导体层的堆叠方向上具有渐变分布。