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公开(公告)号：US20230397514A1
公开(公告)日：2023-12-07
申请号：US17804912
申请日：2022-06-01
发明人： Min Gyu Sung , Soon-Cheon Seo , CHANRO PARK
CPC分类号： H01L45/1273 , H01L45/1675 , H01L45/146 , H01L45/1246 , H01L27/2436
摘要： A method of manufacturing an RRAM cell includes forming a first wire, forming an insulator on the first wire, the insulator having a pore and an insulator surface, and forming a first electrode layer on the first wire and the insulator, the first electrode having an electrode surface. The method further includes recessing the first electrode layer such that the electrode surface is recessed toward the first wire from the insulator surface, forming a switching layer on the insulator and the first electrode, and forming a second electrode on the switching layer.
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公开(公告)号：US11659779B2
公开(公告)日：2023-05-23
申请号：US16977411
申请日：2019-03-08
发明人： Wen Xiao , Wendong Song , Jun Ding , Ernult Franck Gerard
CPC分类号： H01L45/1273 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/16
摘要： Various embodiments may provide a memory cell. The memory cell may include an active electrode including an active electrode material. The memory cell may also include a first noble electrode contact with the active electrode, the first noble electrode being a patterned electrode including a noble electrode material. The memory cell may further include a resistive switching layer in contact with the active electrode and the first noble electrode. The memory cell may additionally include a second noble electrode including a noble electrode material, the second noble electrode in contact with the resistive switching layer.
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公开(公告)号：US20180248117A1
公开(公告)日：2018-08-30
申请号：US15962546
申请日：2018-04-25
发明人： Alexander Alexandrovich Bessonov , Dmitrii Igorevich Petukhov , Marina Nikolaevna Kirikova , Mark Bailey , Tapani Ryhanen
CPC分类号： H01L45/1233 , H01G7/06 , H01L45/08 , H01L45/1253 , H01L45/1273 , H01L45/141 , H01L45/142 , H01L45/146 , H01L45/16 , H01L45/1608 , H01L45/1641
摘要： A device is disclosed which comprises a first electrode (101), a second electrode (104) spaced from the first electrode, a switching region (102) positioned between the first electrode and the second electrode, and an intermediate region (103) positioned between the switching region and the second electrode, wherein the intermediate region is in electrical contact with the switching region and the second electrode. Preferably, the intermediate region comprises metal nanowires (105) in a polymer matrix, and the device is a memristor or a memcapacitor. In the latter case, the switching region comprises a conductive material (106) and an insulating material (107).
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公开(公告)号：US20180069051A1
公开(公告)日：2018-03-08
申请号：US15697203
申请日：2017-09-06
发明人： Makoto UEKI , Takashi HASE
CPC分类号： H01L27/249 , H01L27/101 , H01L27/2436 , H01L43/12 , H01L45/08 , H01L45/1266 , H01L45/1273 , H01L45/146 , H01L45/1633
摘要： A resistance change element includes first and second electrodes spaced apart from each other, a metal material layer adjacent to the first electrode, an oxide layer adjacent to each of the metal material layer and the first electrode, and a resistance change layer disposed continuously between the second and first electrodes and between the second electrode and the oxide layer. The resistance change layer is made of a metal oxide. The metal material layer is made of a metal or a metal compound. The oxide layer is made of an oxide of the material forming the metal material layer. The first electrode is made of ruthenium, ruthenium oxide, iridium, iridium oxide, platinum, gold, or copper. A free energy of oxide formation of the oxide forming the oxide layer is higher than a free energy of oxide formation of the oxide forming the resistance change layer.
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公开(公告)号：US20180047899A1
公开(公告)日：2018-02-15
申请号：US15432346
申请日：2017-02-14
发明人： HIDEKI HORII , SEONG-GEON PARK , DONG-HO AHN , JUNG-MOO LEE
CPC分类号： H01L45/1683 , H01L27/2427 , H01L27/2463 , H01L27/2481 , H01L45/06 , H01L45/065 , H01L45/1233 , H01L45/126 , H01L45/1273 , H01L45/144
摘要： A variable resistance memory device includes first conductive lines positioned above a substrate. Each of the first conductive lines extends in a first direction and a second direction. Second conductive lines extend in the first direction and the second direction. The second conductive lines are positioned above the first conductive lines. A memory is positioned between the first and second conductive lines. The memory unit overlaps the first and second conductive lines in a third direction. The memory unit includes a first electrode, a variable resistance pattern positioned on the first electrode, and a second electrode positioned on the variable resistance pattern. A selection pattern is positioned on each memory unit. A third electrode is positioned above the selection pattern. The third electrode is in direct contact with a lower surface of each of the second conductive lines.
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公开(公告)号：US09865813B2
公开(公告)日：2018-01-09
申请号：US14952559
申请日：2015-11-25
发明人： Paul Fest
CPC分类号： H01L45/1273 , H01L27/2463 , H01L45/08 , H01L45/085 , H01L45/122 , H01L45/142 , H01L45/144 , H01L45/145 , H01L45/146 , H01L45/16 , H01L45/1675
摘要： A method of forming a resistive memory cell, e.g., CBRAM or ReRAM, includes forming a bottom electrode layer, forming an oxide region of an exposed area of the bottom electrode, removing a region of the bottom electrode layer proximate the oxide region to form a bottom electrode having a pointed tip or edge region. An electrically insulating mini-spacer region is formed adjacent the bottom electrode, and an electrolyte region and top electrode are formed over the bottom electrode and mini-spacer element(s) to define a memory element. The memory element defines a conductive filament/vacancy chain path from the bottom electrode pointed tip region to the top electrode via the electrolyte region. The mini-spacer elements decreases the effective area, or “confinement zone,” for the conductive filament/vacancy chain path, which may improve the device characteristics, and may provide an improvement over techniques that rely on enhanced electric field forces.
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公开(公告)号：US20170345870A1
公开(公告)日：2017-11-30
申请号：US15291203
申请日：2016-10-12
发明人： Po-Hao Tseng , Dai-Ying Lee , Erh-Kun Lai
CPC分类号： H01L27/2436 , H01L45/122 , H01L45/1233 , H01L45/1273 , H01L45/145 , H01L45/146 , H01L45/16 , H01L45/1608
摘要： A resistive memory includes a semiconductor substrate, a dielectric layer, an insulating layer and a metal electrode layer. The semiconductor substrate has a top surface and a recess extending downwards into the semiconductor substrate from the top surface. The dielectric layer is disposed on the semiconductor substrate and has a first through-hole aligning the recess. The insulating layer is disposed in the first through-hole and the recess. The metal electrode layer is disposed on the insulating layer by which the metal electrode layer is isolated from the semiconductor substrate.
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公开(公告)号：US09831289B2
公开(公告)日：2017-11-28
申请号：US14325289
申请日：2014-07-07
申请人： Crossbar, Inc.
发明人： Scott Brad Herner
CPC分类号： H01L27/2463 , H01L45/085 , H01L45/1233 , H01L45/1273 , H01L45/148 , H01L45/16 , H01L45/1683
摘要： A method of forming a disturb-resistant non volatile memory device includes providing a substrate and forming a first dielectric thereon, forming a first strip of material separated from a second strip of material from a first wiring material, and forming a second dielectric thereon to fill a gap between the first and second strips of material. Openings are formed in the second dielectric exposing portions of the first wiring material. Filing the openings by p+ polysilicon contact material, and then an undoped amorphous silicon material, and then a metal material. A second wiring structure is formed thereon to contact the metal material in the openings. Resistive switching cells are formed from the first wiring structure, the second wiring structure, the contact material, the undoped amorphous silicon material, and the metal material.
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公开(公告)号：US09741768B1
公开(公告)日：2017-08-22
申请号：US15087980
申请日：2016-03-31
IPC分类号： H01L27/11521 , H01L27/24 , H01L45/00 , H01L21/02
CPC分类号： H01L27/249 , H01L21/02491 , H01L27/11521 , H01L27/2454 , H01L45/04 , H01L45/085 , H01L45/1226 , H01L45/1233 , H01L45/1266 , H01L45/1273 , H01L45/145 , H01L45/146 , H01L45/16 , H01L45/1608
摘要： A method is provided that includes forming a vertical bit line disposed in a first direction above a substrate, forming a multi-layer word line disposed in a second direction above the substrate, the second direction perpendicular to the first direction, and forming a memory cell including a nonvolatile memory material at an intersection of the vertical bit line and the multi-layer word line. The multi-layer word line includes a first conductive material layer and a second conductive material layer disposed above the first conductive material layer. The memory cell includes a working cell area encompassed by an intersection of the first conductive material layer and the nonvolatile memory material.
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公开(公告)号：US09685607B2
公开(公告)日：2017-06-20
申请号：US14637139
申请日：2015-03-03
发明人： Yoshio Ozawa
CPC分类号： H01L45/085 , H01L27/2481 , H01L27/249 , H01L45/1226 , H01L45/1233 , H01L45/1266 , H01L45/1273 , H01L45/145 , H01L45/1616
摘要： A non-volatile semiconductor memory device according to an embodiment includes a plurality of first wiring lines that extend in a first direction, a plurality of second wiring lines that extend in a second direction intersecting the first direction to cross the first wiring lines, and memory cells, each of which is provided at a portion where the first wiring line crosses the second wiring line. The memory cell includes a variable resistance layer in the space between the wiring lines where the first wiring line crosses the second wiring line, a seam in the variable resistance layer extending in a direction between the first wiring layer and the second wiring layer, and a metal supply layer that comes in contact with the variable resistance layer and the seam.
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