公开(公告)号：US10009197B1

公开(公告)日：2018-06-26

申请号：US15289680

申请日：2016-10-10

Applicant: Xilinx, Inc.

Inventor： Terence J. Magee ,  Asim A. Patel

IPC: H04L25/03 ,  H04L7/00

CPC classification number: H04L7/0037 ,  G11C7/1087 ,  G11C7/1093 ,  G11C2207/2254 ,  H03K19/1774 ,  H04L25/03878

Abstract: An intersymbol interference (ISI) compensation circuit includes a data input for receiving an input data signal including a plurality of bits. An adjustment circuit is configured to adjust bit periods of the bits to generate a first adjusted signal and a second adjusted signal. A sampling circuit is configured to generate a first sample signal by sampling the first adjusted signal, and generate a second sample signal by sampling the second adjusted signal. A decision generation circuit is configured to provide a first decision for a first bit. The first decision provides a chosen adjusted signal that is one of the first and second adjusted signals. A selection circuit is configured to determine a compensated value of the first bit based on a chosen sample signal that is one of the first and second sample signals. The chosen sample signal is generated by sampling the chosen adjusted signal.

公开(公告)号：US20180294802A1

公开(公告)日：2018-10-11

申请号：US15480283

申请日：2017-04-05

Applicant: Xilinx, Inc.

Inventor： Richard W. Swanson ,  Terence J. Magee ,  Qi Zhang ,  Srinivas Vura

IPC: H03K5/06 ,  G11C11/4076 ,  H04L7/00

Abstract: An example method of calibrating a source-synchronous system includes: performing initial calibration of a source-synchronous receiver, which is configured to receive data signals and a strobe, to determine an initial strobe delay and initial data delays; setting a strobe delay circuit that delays the strobe to have the initial strobe delay and data delay circuits that delay the data signals to have the initial data delays; measuring first data eye margins of the data signals at a first time; calculating metrics for the data signals based on the first data eye margins; and measuring second data eye margins of the data signals at a second time; and updating the data delay circuits and the strobe delay circuit based on the second data eye margins and the metrics.

公开(公告)号：US09330749B1

公开(公告)日：2016-05-03

申请号：US14519562

申请日：2014-10-21

Applicant: Xilinx, Inc.

Inventor： Dhruv Choksey ,  Terence J. Magee

IPC: G11C11/4063

CPC classification number: G11C11/4063 ,  G06F13/1689 ,  G11C11/4076 ,  Y02D10/14

Abstract: In an example, a memory control device includes an output circuit, an output delay unit, and a write-levelization controller. The output circuit is coupled to provide an output signal comprising a data signal or data strobe signal for a synchronous dynamic random access memory (SDRAM) system having a plurality of ranks. The output delay unit is coupled to apply an output delay to a bitstream to be transmitted to generate the output signal. The output delay includes an aggregate of a de-skew delay and a write-levelization delay. The write-levelization delay controller is coupled to adjust the write-levelization delay for each write transaction to the SDRAM system of a plurality of write transactions based on a selected rank of the plurality of ranks. The de-skew delay is the same across the plurality of ranks for each of the plurality of write transactions.

Abstract translation: 在一个示例中，存储器控制装置包括输出电路，输出延迟单元和写平均化控制器。 输出电路被耦合以提供包括用于具有多个等级的同步动态随机存取存储器（SDRAM）系统的数据信号或数据选通信号的输出信号。 输出延迟单元被耦合以将输出延迟施加到要发送的比特流以产生输出信号。 输出延迟包括去偏移延迟和写平均化延迟的汇总。 写级别化延迟控制器被耦合以基于多个等级的所选等级将针对每个写入事务的写入级别延迟调整到多个写入事务的SDRAM系统。 对于多个写入事务中的每一个，多个等级中的去偏斜延迟是相同的。

公开(公告)号：US09355696B1

公开(公告)日：2016-05-31

申请号：US14534487

申请日：2014-11-06

Applicant: Xilinx, Inc.

Inventor： Terence J. Magee ,  Xiaoqian Zhang

IPC: G11C7/10 ,  G11C7/22 ,  H03K5/14 ,  G11C11/00

CPC classification number: G11C7/222 ,  G06F13/4243 ,  G11C11/005 ,  H03K5/14

Abstract: In an example, a control device includes a data path, a clock path, a multiplexing circuit, and a calibration unit. The data path comprises a data delay unit coupled to a data input of a sampling circuit. The clock path comprises a clock delay unit coupled to a clock input of the sampling circuit. The multiplexing circuit selectively couples a reference clock or a data bus to an input of the data delay unit, and selectively couples the reference clock or a source clock to an input of the clock delay unit. The calibration unit is coupled to a data output of the sampling circuit. The calibration unit is operable to adjust delay values of the data delay unit and the clock delay unit based on the data output of the sampling circuit to establish and maintain a relative delay between the data path and the clock path.

Abstract translation: 在一个示例中，控制装置包括数据路径，时钟路径，复用电路和校准单元。 数据路径包括耦合到采样电路的数据输入的数据延迟单元。 时钟路径包括耦合到采样电路的时钟输入的时钟延迟单元。 多路复用电路将参考时钟或数据总线选择性地耦合到数据延迟单元的输入，并且将参考时钟或源时钟选择性地耦合到时钟延迟单元的输入。 校准单元耦合到采样电路的数据输出。 校准单元可操作以基于采样电路的数据输出来调整数据延迟单元和时钟延迟单元的延迟值，以建立和维持数据路径与时钟路径之间的相对延迟。

公开(公告)号：US09281049B1

公开(公告)日：2016-03-08

申请号：US14525875

申请日：2014-10-28

Applicant: Xilinx, Inc.

Inventor： Terence J. Magee ,  Jayant Mittal

IPC: G11C7/10 ,  G11C11/409 ,  G11C11/4076 ,  G11C7/22

CPC classification number: G11C11/409 ,  G06F13/1694 ,  G11C7/22 ,  G11C11/4076

Abstract: Systems, devices, and circuits for source-synchronous memory interfaces are disclosed. For example, a device includes a first NAND gate with an input for receiving a serial mode enable signal. In addition, the device also includes a second NAND gate with an input for receiving a forwarded strobe signal and an input for receiving an output of the first NAND gate. The device also includes a third NAND gate with an input for receiving a data strobe signal, and an XNOR gate with an input for receiving an output of the second NAND gate and an input for receiving an output of the third NAND gate.

Abstract translation: 公开了用于源同步存储器接口的系统，设备和电路。 例如，设备包括具有用于接收串行模式使能信号的输入的第一NAND门。 此外，该装置还包括具有用于接收转发的选通信号的输入的第二与非门和用于接收第一NAND门的输出的输入。 该器件还包括具有用于接收数据选通信号的输入的第三NAND门和具有用于接收第二NAND门的输出的输入的XNOR门和用于接收第三NAND门的输出的输入。

公开(公告)号：US09224444B1

公开(公告)日：2015-12-29

申请号：US14523781

申请日：2014-10-24

Applicant: Xilinx, Inc.

Inventor： Terence J. Magee ,  Sathappan Ravi ,  Dhruv Choksey

IPC: G11C8/00 ,  G11C7/22 ,  G11C7/10 ,  G11C8/18

CPC classification number: G11C7/222 ,  G06F13/1689 ,  G11C7/1072 ,  G11C7/1093 ,  G11C8/18

Abstract: A method, non-transitory computer readable medium and apparatus for synchronizing a clock signal data path, a write strobe signal data path and a write data signal data path are disclosed. The method determines an amount of phase shift between the clock signal data path and the write strobe signal data path and between the clock signal data path and the write data signal data path, gates a clock signal to generate strobe clock signals that are phase shifted by at least one phase shift, applies a fine phase shift to the strobe clock signals where the strobe clock signals have an overall phase shift that is approximately equal to the amount of phase shift, and synchronizes a launch of the clock signal data path, the write strobe signal data path, and the write data signal data path using the strobe clock signals with the overall phase shift.

Abstract translation: 公开了一种用于同步时钟信号数据路径，写入选通信号数据路径和写入数据信号数据路径的方法，非暂时性计算机可读介质和装置。 该方法确定时钟信号数据路径和写入选通信号数据路径之间以及时钟信号数据路径与写入数据信号数据路径之间的相移量，对时钟信号进行门控，产生相位偏移的选通时钟信号 至少一个相移，对选通时钟信号施加精细的相移，其中选通时钟信号具有大致相等于相移量的总相移，同步启动时钟信号数据路径，写入 选通信号数据路径，以及使用具有整体相移的选通时钟信号的写入数据信号数据路径。

公开(公告)号：US20160133305A1

公开(公告)日：2016-05-12

申请号：US14534487

申请日：2014-11-06

Applicant: XILINX, INC.

Inventor： Terence J. Magee ,  Xiaoqian Zhang

IPC: G11C7/22 ,  H03K5/14

CPC classification number: G11C7/222 ,  G06F13/4243 ,  G11C11/005 ,  H03K5/14

Abstract: In an example, a control device includes a data path, a clock path, a multiplexing circuit, and a calibration unit. The data path comprises a data delay unit coupled to a data input of a sampling circuit. The clock path comprises a clock delay unit coupled to a clock input of the sampling circuit. The multiplexing circuit selectively couples a reference clock or a data bus to an input of the data delay unit, and selectively couples the reference clock or a source clock to an input of the clock delay unit. The calibration unit is coupled to a data output of the sampling circuit. The calibration unit is operable to adjust delay values of the data delay unit and the clock delay unit based on the data output of the sampling circuit to establish and maintain a relative delay between the data path and the clock path.

Abstract translation: 在一个示例中，控制装置包括数据路径，时钟路径，复用电路和校准单元。 数据路径包括耦合到采样电路的数据输入的数据延迟单元。 时钟路径包括耦合到采样电路的时钟输入的时钟延迟单元。 多路复用电路将参考时钟或数据总线选择性地耦合到数据延迟单元的输入，并且将参考时钟或源时钟选择性地耦合到时钟延迟单元的输入。 校准单元耦合到采样电路的数据输出。 校准单元可操作以基于采样电路的数据输出来调整数据延迟单元和时钟延迟单元的延迟值，以建立和维持数据路径与时钟路径之间的相对延迟。

公开(公告)号：US09324409B1

公开(公告)日：2016-04-26

申请号：US14534493

申请日：2014-11-06

Applicant: Xilinx, Inc.

Inventor： Terence J. Magee ,  Jayant Mittal

IPC: G11C8/16 ,  G11C11/409

CPC classification number: G11C7/1066

Abstract: A method, non-transitory computer readable medium and circuit for gating a strobe (DQS) signal are disclosed. The method sends a read command to a memory, sends a strobe clock signal after the read command is sent and before the DQS signal is received from the memory, wherein the strobe clock signal comprises a duration equal to a duration of the DQS signal, gates the DQS signal based on the strobe clock signal to generate a positively gated strobe signal for indicating a rising edge of the DQS signal, wherein the gating is performed during a pre-amble of the DQS signal and generates a negatively gated strobe signal based on the positively gated strobe signal for indicating a falling edge of the DQS signal.

Abstract translation: 公开了一种用于选通选通（DQS）信号的方法，非暂时性计算机可读介质和电路。 该方法向存储器发送读命令，在读命令发送之后并且在从存储器接收到DQS信号之前发送选通时钟信号，其中选通时钟信号包括等于DQS信号持续时间的持续时间，门 所述DQS信号基于所述选通时钟信号以产生用于指示所述DQS信号的上升沿的肯定选通信号，其中所述门控在所述DQS信号的前同步码期间执行，并且基于所述DQS信号产生负门控选通信号 用于指示DQS信号的下降沿的正门控选通信号。

公开(公告)号：US10103718B1

公开(公告)日：2018-10-16

申请号：US15480283

申请日：2017-04-05

Applicant: Xilinx, Inc.

Inventor： Richard W. Swanson ,  Terence J. Magee ,  Qi Zhang ,  Srinivas Vura

IPC: G11C11/407 ,  G11C7/22 ,  H03K5/134 ,  G11C7/00 ,  G11C7/10 ,  H03K5/06 ,  G11C11/4076 ,  H04L7/00 ,  H03K5/00

Abstract: An example method of calibrating a source-synchronous system includes: performing initial calibration of a source-synchronous receiver, which is configured to receive data signals and a strobe, to determine an initial strobe delay and initial data delays; setting a strobe delay circuit that delays the strobe to have the initial strobe delay and data delay circuits that delay the data signals to have the initial data delays; measuring first data eye margins of the data signals at a first time; calculating metrics for the data signals based on the first data eye margins; and measuring second data eye margins of the data signals at a second time; and updating the data delay circuits and the strobe delay circuit based on the second data eye margins and the metrics.

公开(公告)号：US20160111139A1

公开(公告)日：2016-04-21

申请号：US14519562

申请日：2014-10-21

Applicant: XILINX, INC.

Inventor： Dhruv Choksey ,  Terence J. Magee

IPC: G11C11/4063

CPC classification number: G11C11/4063 ,  G06F13/1689 ,  G11C11/4076 ,  Y02D10/14

Abstract: In an example, a memory control device includes an output circuit, an output delay unit, and a write-levelization controller. The output circuit is coupled to provide an output signal comprising a data signal or data strobe signal for a synchronous dynamic random access memory (SDRAM) system having a plurality of ranks. The output delay unit is coupled to apply an output delay to a bitstream to be transmitted to generate the output signal. The output delay includes an aggregate of a de-skew delay and a write-levelization delay. The write-levelization delay controller is coupled to adjust the write-levelization delay for each write transaction to the SDRAM system of a plurality of write transactions based on a selected rank of the plurality of ranks. The de-skew delay is the same across the plurality of ranks for each of the plurality of write transactions.

Abstract translation: 在一个示例中，存储器控制装置包括输出电路，输出延迟单元和写平均化控制器。 输出电路被耦合以提供包括用于具有多个等级的同步动态随机存取存储器（SDRAM）系统的数据信号或数据选通信号的输出信号。 输出延迟单元被耦合以将输出延迟施加到要发送的比特流以产生输出信号。 输出延迟包括去偏移延迟和写平均化延迟的汇总。 写级别化延迟控制器被耦合以基于多个等级的所选等级将针对每个写入事务的写入级别延迟调整到多个写入事务的SDRAM系统。 对于多个写入事务中的每一个，多个等级中的去偏斜延迟是相同的。