Method and apparatus for VT invariant SDRAM write leveling and fast rank switching
    1.
    发明授权
    Method and apparatus for VT invariant SDRAM write leveling and fast rank switching 有权
    用于VT不变式SDRAM写入调平和快速级别切换的方法和装置

    公开(公告)号:US09224444B1

    公开(公告)日:2015-12-29

    申请号:US14523781

    申请日:2014-10-24

    Applicant: Xilinx, Inc.

    CPC classification number: G11C7/222 G06F13/1689 G11C7/1072 G11C7/1093 G11C8/18

    Abstract: A method, non-transitory computer readable medium and apparatus for synchronizing a clock signal data path, a write strobe signal data path and a write data signal data path are disclosed. The method determines an amount of phase shift between the clock signal data path and the write strobe signal data path and between the clock signal data path and the write data signal data path, gates a clock signal to generate strobe clock signals that are phase shifted by at least one phase shift, applies a fine phase shift to the strobe clock signals where the strobe clock signals have an overall phase shift that is approximately equal to the amount of phase shift, and synchronizes a launch of the clock signal data path, the write strobe signal data path, and the write data signal data path using the strobe clock signals with the overall phase shift.

    Abstract translation: 公开了一种用于同步时钟信号数据路径,写入选通信号数据路径和写入数据信号数据路径的方法,非暂时性计算机可读介质和装置。 该方法确定时钟信号数据路径和写入选通信号数据路径之间以及时钟信号数据路径与写入数据信号数据路径之间的相移量,对时钟信号进行门控,产生相位偏移的选通时钟信号 至少一个相移,对选通时钟信号施加精细的相移,其中选通时钟信号具有大致相等于相移量的总相移,同步启动时钟信号数据路径,写入 选通信号数据路径,以及使用具有整体相移的选通时钟信号的写入数据信号数据路径。

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