公开(公告)号：US20160111139A1

公开(公告)日：2016-04-21

申请号：US14519562

申请日：2014-10-21

Applicant: XILINX, INC.

Inventor： Dhruv Choksey ,  Terence J. Magee

IPC: G11C11/4063

CPC classification number: G11C11/4063 ,  G06F13/1689 ,  G11C11/4076 ,  Y02D10/14

Abstract: In an example, a memory control device includes an output circuit, an output delay unit, and a write-levelization controller. The output circuit is coupled to provide an output signal comprising a data signal or data strobe signal for a synchronous dynamic random access memory (SDRAM) system having a plurality of ranks. The output delay unit is coupled to apply an output delay to a bitstream to be transmitted to generate the output signal. The output delay includes an aggregate of a de-skew delay and a write-levelization delay. The write-levelization delay controller is coupled to adjust the write-levelization delay for each write transaction to the SDRAM system of a plurality of write transactions based on a selected rank of the plurality of ranks. The de-skew delay is the same across the plurality of ranks for each of the plurality of write transactions.

Abstract translation: 在一个示例中，存储器控制装置包括输出电路，输出延迟单元和写平均化控制器。 输出电路被耦合以提供包括用于具有多个等级的同步动态随机存取存储器（SDRAM）系统的数据信号或数据选通信号的输出信号。 输出延迟单元被耦合以将输出延迟施加到要发送的比特流以产生输出信号。 输出延迟包括去偏移延迟和写平均化延迟的汇总。 写级别化延迟控制器被耦合以基于多个等级的所选等级将针对每个写入事务的写入级别延迟调整到多个写入事务的SDRAM系统。 对于多个写入事务中的每一个，多个等级中的去偏斜延迟是相同的。

公开(公告)号：US09330749B1

公开(公告)日：2016-05-03

申请号：US14519562

申请日：2014-10-21

Applicant: Xilinx, Inc.

Inventor： Dhruv Choksey ,  Terence J. Magee

IPC: G11C11/4063

CPC classification number: G11C11/4063 ,  G06F13/1689 ,  G11C11/4076 ,  Y02D10/14

Abstract: In an example, a memory control device includes an output circuit, an output delay unit, and a write-levelization controller. The output circuit is coupled to provide an output signal comprising a data signal or data strobe signal for a synchronous dynamic random access memory (SDRAM) system having a plurality of ranks. The output delay unit is coupled to apply an output delay to a bitstream to be transmitted to generate the output signal. The output delay includes an aggregate of a de-skew delay and a write-levelization delay. The write-levelization delay controller is coupled to adjust the write-levelization delay for each write transaction to the SDRAM system of a plurality of write transactions based on a selected rank of the plurality of ranks. The de-skew delay is the same across the plurality of ranks for each of the plurality of write transactions.

Abstract translation: 在一个示例中，存储器控制装置包括输出电路，输出延迟单元和写平均化控制器。 输出电路被耦合以提供包括用于具有多个等级的同步动态随机存取存储器（SDRAM）系统的数据信号或数据选通信号的输出信号。 输出延迟单元被耦合以将输出延迟施加到要发送的比特流以产生输出信号。 输出延迟包括去偏移延迟和写平均化延迟的汇总。 写级别化延迟控制器被耦合以基于多个等级的所选等级将针对每个写入事务的写入级别延迟调整到多个写入事务的SDRAM系统。 对于多个写入事务中的每一个，多个等级中的去偏斜延迟是相同的。

公开(公告)号：US09224444B1

公开(公告)日：2015-12-29

申请号：US14523781

申请日：2014-10-24

Applicant: Xilinx, Inc.

Inventor： Terence J. Magee ,  Sathappan Ravi ,  Dhruv Choksey

IPC: G11C8/00 ,  G11C7/22 ,  G11C7/10 ,  G11C8/18

CPC classification number: G11C7/222 ,  G06F13/1689 ,  G11C7/1072 ,  G11C7/1093 ,  G11C8/18

Abstract: A method, non-transitory computer readable medium and apparatus for synchronizing a clock signal data path, a write strobe signal data path and a write data signal data path are disclosed. The method determines an amount of phase shift between the clock signal data path and the write strobe signal data path and between the clock signal data path and the write data signal data path, gates a clock signal to generate strobe clock signals that are phase shifted by at least one phase shift, applies a fine phase shift to the strobe clock signals where the strobe clock signals have an overall phase shift that is approximately equal to the amount of phase shift, and synchronizes a launch of the clock signal data path, the write strobe signal data path, and the write data signal data path using the strobe clock signals with the overall phase shift.

Abstract translation: 公开了一种用于同步时钟信号数据路径，写入选通信号数据路径和写入数据信号数据路径的方法，非暂时性计算机可读介质和装置。 该方法确定时钟信号数据路径和写入选通信号数据路径之间以及时钟信号数据路径与写入数据信号数据路径之间的相移量，对时钟信号进行门控，产生相位偏移的选通时钟信号 至少一个相移，对选通时钟信号施加精细的相移，其中选通时钟信号具有大致相等于相移量的总相移，同步启动时钟信号数据路径，写入 选通信号数据路径，以及使用具有整体相移的选通时钟信号的写入数据信号数据路径。