公开(公告)号：US10009197B1

公开(公告)日：2018-06-26

申请号：US15289680

申请日：2016-10-10

Applicant: Xilinx, Inc.

Inventor： Terence J. Magee ,  Asim A. Patel

IPC: H04L25/03 ,  H04L7/00

CPC classification number: H04L7/0037 ,  G11C7/1087 ,  G11C7/1093 ,  G11C2207/2254 ,  H03K19/1774 ,  H04L25/03878

Abstract: An intersymbol interference (ISI) compensation circuit includes a data input for receiving an input data signal including a plurality of bits. An adjustment circuit is configured to adjust bit periods of the bits to generate a first adjusted signal and a second adjusted signal. A sampling circuit is configured to generate a first sample signal by sampling the first adjusted signal, and generate a second sample signal by sampling the second adjusted signal. A decision generation circuit is configured to provide a first decision for a first bit. The first decision provides a chosen adjusted signal that is one of the first and second adjusted signals. A selection circuit is configured to determine a compensated value of the first bit based on a chosen sample signal that is one of the first and second sample signals. The chosen sample signal is generated by sampling the chosen adjusted signal.