公开(公告)号：US10659215B1

公开(公告)日：2020-05-19

申请号：US16135653

申请日：2018-09-19

Applicant: Xilinx, Inc.

Inventor： Xiaobao Wang ,  Arvind R. Bomdica ,  Balakrishna Jayadev ,  Richard W. Swanson

IPC: G11C7/00 ,  G11C11/00 ,  H04L7/00 ,  G11C7/22 ,  H03L7/081 ,  G11C7/10 ,  G11C29/50

Abstract: Methods and apparatus relate to a 1-to-2 memory interface deserializer circuit that, in a training mode, independently positions even and odd strobes in respective even and odd data windows. In an illustrative example, the deserializer circuit may receive a data signal that encodes even and odd data streams on the rising (even) and falling (odd) edges of a strobe clock signal. During a training mode, the deserializer circuit may independently determine, for example, an optimal temporal delay for each of the even strobe and the odd strobe. Adjustable delay lines dedicated to each of the even and odd strobe signals may simultaneously detect valid data window edges to permit determination of a desired delay to optimally position the strobe signals. Various embodiments may advantageously reduce jitter associated with asymmetric strobe and/or data signals to achieve a predetermined specification (e.g., timing margins) within the corresponding data windows.

公开(公告)号：US20180294802A1

公开(公告)日：2018-10-11

申请号：US15480283

申请日：2017-04-05

Applicant: Xilinx, Inc.

Inventor： Richard W. Swanson ,  Terence J. Magee ,  Qi Zhang ,  Srinivas Vura

IPC: H03K5/06 ,  G11C11/4076 ,  H04L7/00

Abstract: An example method of calibrating a source-synchronous system includes: performing initial calibration of a source-synchronous receiver, which is configured to receive data signals and a strobe, to determine an initial strobe delay and initial data delays; setting a strobe delay circuit that delays the strobe to have the initial strobe delay and data delay circuits that delay the data signals to have the initial data delays; measuring first data eye margins of the data signals at a first time; calculating metrics for the data signals based on the first data eye margins; and measuring second data eye margins of the data signals at a second time; and updating the data delay circuits and the strobe delay circuit based on the second data eye margins and the metrics.

公开(公告)号：US09453870B1

公开(公告)日：2016-09-27

申请号：US14252958

申请日：2014-04-15

Applicant: Xilinx, Inc.

Inventor： Amitava Majumdar ,  Richard W. Swanson ,  Anna W. Wong ,  Suraj Ethirajan ,  Asim A. Bajwa ,  Jongheon Jeong

IPC: G01R31/14 ,  G01R31/02

CPC classification number: G01R31/021 ,  G01R19/2513 ,  G01R31/025 ,  G01R31/2853

Abstract: In an apparatus relating generally to an IC die, the IC die has a regulated power supply, a power supply grid, and a test circuit. The regulated power supply is biased between a source supply node and a source ground node, which are externally accessible nodes of the IC die. An internal supply node of the power supply grid is coupled to the regulated power supply. The test circuit is coupled to the internal supply node of the power supply grid. The test circuit is configured to test for at least one short in the power supply grid. The test circuit is configured to limit power through the power supply grid to less than that of a probe tip tolerance. The test circuit is configured to test for the at least one short in presence of background current leakage of the power supply grid.

Abstract translation: 在与IC芯片大致相关的装置中，IC芯片具有稳压电源，电源网格和测试电路。 稳压电源在源电源节点和源极接地节点之间偏置，源极接地节点是IC芯片的外部可访问节点。 电源网格的内部供电节点耦合到稳压电源。 测试电路耦合到电源网格的内部供电节点。 测试电路被配置为测试电源网格中的至少一个短路。 测试电路被配置为将电源网格的电力限制为小于探针尖端公差的电力。 测试电路被配置为在存在电源网格的背景电流泄漏的情况下测试至少一个短路。

公开(公告)号：US12130769B2

公开(公告)日：2024-10-29

申请号：US18073327

申请日：2022-12-01

Applicant: XILINX, INC.

Inventor： David P. Schultz ,  Richard W. Swanson

IPC: G06F13/42

CPC classification number: G06F13/4291 ,  G06F2213/0016

Abstract: An integrated circuit (IC) device includes a first IC chip, a second IC chip, and a chip-to-chip interface connected between the first IC chip and the second IC chip. The chip-to-chip interface communicates an interface clock signal and a logic clock signal between the first IC chip and the second IC chip. A frequency of the interface clock signal is a multiple of a frequency of the logic clock signal.

公开(公告)号：US10454418B1

公开(公告)日：2019-10-22

申请号：US15432781

申请日：2017-02-14

Applicant: Xilinx, Inc.

Inventor： Ankur Jain ,  Jaeseo Lee ,  Richard W. Swanson

IPC: H03B1/00 ,  H03K3/03 ,  H03L7/099 ,  G05F1/46 ,  G05F1/575

Abstract: In an example, a voltage-controlled oscillator (VCO) includes: an oscillator having a supply input; and a voltage regulator, coupled to the supply input. The voltage regulator includes: a first transistor and a second transistor providing a first source-coupled transistor pair, and a third transistor and a fourth transistor providing a second source-coupled transistor pair; an active load coupled to drains of the first, second, third, and fourth transistors; a first current source coupled to sources of the first and second transistors, and a second current source coupled to sources of the third and fourth transistors; a fifth transistor having a source and a drain coupled to the source and the drain, respectively, of the first transistor; and a sixth transistor having a source and a drain coupled to the source and the drain, respectively, of the third transistor.

公开(公告)号：US08884804B1

公开(公告)日：2014-11-11

申请号：US14089222

申请日：2013-11-25

Applicant: Xilinx, Inc.

Inventor： Amitava Majumdar ,  Siva Charan Nimmagadda ,  Baanurathan Sadasivam ,  Richard W. Swanson ,  Yohan Frans

IPC: H03M1/50 ,  H03M1/12 ,  H03L7/081 ,  H03L7/087 ,  H03L7/089 ,  H03M1/00

CPC classification number: G04F10/005 ,  H03L7/00 ,  H03L7/0814 ,  H03L7/087 ,  H03L7/0891 ,  H03L7/0895 ,  H03M1/00 ,  H03M1/12 ,  H03M2201/4233

Abstract: An apparatus relating generally to time-to-digital conversion is disclosed. In this apparatus, a time-to-digital converter is coupled to a period sensor. The period sensor includes a pulse generator to generate a pulse. An integrator of the period sensor is coupled to receive the pulse to generate an analog voltage signal responsive to the pulse. The time-to-digital converter includes an analog-to-digital converter coupled to provide a digital signal associated with the analog voltage signal.

Abstract translation: 公开了一种与时间 - 数字转换相关的装置。 在该装置中，时间 - 数字转换器耦合到周期传感器。 周期传感器包括产生脉冲的脉冲发生器。 耦合周期传感器的积分器以接收脉冲以产生响应脉冲的模拟电压信号。 时间 - 数字转换器包括耦合以提供与模拟电压信号相关联的数字信号的模拟 - 数字转换器。

公开(公告)号：US12273106B2

公开(公告)日：2025-04-08

申请号：US18073288

申请日：2022-12-01

Applicant: XILINX, INC.

Inventor： David P. Schultz ,  Richard W. Swanson

IPC: H03K19/018 ,  G06F13/42 ,  H03K19/0185 ,  H03K19/17736 ,  H03K21/02

Abstract: An integrated circuit (IC) device includes a first IC chip, a second IC chip, and a chip-to-chip interface connected between the first IC chip and the second IC chip. The chip-to-chip interface communicates an interface clock signal and a logic clock signal between the first IC chip and the second IC chip. The interface clock signal is synchronous with a data signal received by one of the first IC chip and the second IC chip. The logic clock signal is asynchronous with the data signal.

公开(公告)号：US09559704B1

公开(公告)日：2017-01-31

申请号：US14938741

申请日：2015-11-11

Applicant: Xilinx, Inc.

Inventor： Anna W. Wong ,  Ankur Jain ,  Richard W. Swanson

IPC: H03L7/08 ,  H03L7/197

CPC classification number: H03L7/1974 ,  H03L7/18

Abstract: In an example, operating a PLL circuit includes generating an error signal in response to comparison of a reference clock signal having a reference frequency and a feedback clock signal having a feedback frequency, generating a plurality of clock signals having an output frequency based on the error signal, and generating the feedback clock signal from the plurality of clock signals based on a first divider value and a control value derived from a second divider value. Operating the PLL circuit further includes multiplying each of a first integer value and a first fractional value by a power of two to generate a second integer value and a second fractional value, respectively, generating the second divider value using a sigma-delta modulator (SDM) based on the second integer value and the second fractional value, and dividing the second divider value by the power of two to generate the first divider value.

Abstract translation: 在一个示例中，操作PLL电路包括响应于具有参考频率的参考时钟信号和具有反馈频率的反馈时钟信号的比较来产生误差信号，产生具有基于误差的输出频率的多个时钟信号 信号，并且基于第一分频器值和从第二分频值导出的控制值从多个时钟信号产生反馈时钟信号。 操作PLL电路还包括将第一整数值和第一分数值中的每一个乘以2的幂来分别产生第二整数值和第二分数值，以使用Σ-Δ调制器（SDM）产生第二分频器值 ），并且将第二分频值除以二的幂来产生第一分频值。

公开(公告)号：US10103718B1

公开(公告)日：2018-10-16

申请号：US15480283

申请日：2017-04-05

Applicant: Xilinx, Inc.

Inventor： Richard W. Swanson ,  Terence J. Magee ,  Qi Zhang ,  Srinivas Vura

IPC: G11C11/407 ,  G11C7/22 ,  H03K5/134 ,  G11C7/00 ,  G11C7/10 ,  H03K5/06 ,  G11C11/4076 ,  H04L7/00 ,  H03K5/00

Abstract: An example method of calibrating a source-synchronous system includes: performing initial calibration of a source-synchronous receiver, which is configured to receive data signals and a strobe, to determine an initial strobe delay and initial data delays; setting a strobe delay circuit that delays the strobe to have the initial strobe delay and data delay circuits that delay the data signals to have the initial data delays; measuring first data eye margins of the data signals at a first time; calculating metrics for the data signals based on the first data eye margins; and measuring second data eye margins of the data signals at a second time; and updating the data delay circuits and the strobe delay circuit based on the second data eye margins and the metrics.