公开(公告)号：US09768029B2

公开(公告)日：2017-09-19

申请号：US15169472

申请日：2016-05-31

Applicant: United Microelectronics Corp.

Inventor： Chun-Hsien Lin ,  Min-Hsien Chen

IPC: H01L21/28 ,  H01L29/49 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/285 ,  H01L29/51 ,  H01L29/165

CPC classification number: H01L21/28088 ,  H01L21/2855 ,  H01L21/823842 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66636

Abstract: A method of forming a semiconductor device is disclosed. A substrate having a dielectric layer thereon is provided. The dielectric layer has a gate trench therein and a gate dielectric layer is formed on a bottom of the gate trench. A work function metal layer and a top barrier layer are sequentially formed in the gate trench. A treatment is performed to the top barrier layer so as to form a silicon-containing top barrier layer. A low-resistivity metal layer is formed in the gate trench.

公开(公告)号：US09384984B2

公开(公告)日：2016-07-05

申请号：US14017001

申请日：2013-09-03

Applicant: United Microelectronics Corp.

Inventor： Chun-Hsien Lin ,  Min-Hsien Chen

IPC: H01L29/76 ,  H01L21/28 ,  H01L29/49 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/51 ,  H01L29/165

CPC classification number: H01L21/28088 ,  H01L21/2855 ,  H01L21/823842 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66636

Abstract: A method of forming a semiconductor device is disclosed. A substrate having a dielectric layer thereon is provided. The dielectric layer has a gate trench therein and a gate dielectric layer is formed on a bottom of the gate trench. A work function metal layer and a top barrier layer are sequentially formed in the gate trench. A treatment is performed to the top barrier layer so as to form a silicon-containing top barrier layer. A low-resistivity metal layer is formed in the gate trench.

Abstract translation: 公开了一种形成半导体器件的方法。 提供其上具有介电层的基板。 电介质层在其中具有栅极沟槽，栅极电介质层形成在栅极沟槽的底部。 工作功能金属层和顶部阻挡层依次形成在栅极沟槽中。 对顶部阻挡层进行处理以形成含硅顶部阻挡层。 在栅极沟槽中形成低电阻率金属层。

公开(公告)号：US20150061041A1

公开(公告)日：2015-03-05

申请号：US14017001

申请日：2013-09-03

Applicant: United Microelectronics Corp.

Inventor： Chun-Hsien Lin ,  Min-Hsien Chen

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L21/28088 ,  H01L21/2855 ,  H01L21/823842 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66636

Abstract: A method of forming a semiconductor device is disclosed. A substrate having a dielectric layer thereon is provided. The dielectric layer has a gate trench therein and a gate dielectric layer is formed on a bottom of the gate trench. A work function metal layer and a top barrier layer are sequentially formed in the gate trench. A treatment is performed to the top barrier layer so as to form a silicon-containing top barrier layer. A low-resistivity metal layer is formed in the gate trench.

Abstract translation: 公开了一种形成半导体器件的方法。 提供其上具有介电层的基板。 电介质层在其中具有栅极沟槽，栅极电介质层形成在栅极沟槽的底部。 工作功能金属层和顶部阻挡层依次形成在栅极沟槽中。 对顶部阻挡层进行处理以形成含硅顶部阻挡层。 在栅极沟槽中形成低电阻率金属层。

公开(公告)号：US20140374909A1

公开(公告)日：2014-12-25

申请号：US14480648

申请日：2014-09-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chi-Mao Hsu ,  Hsin-Fu Huang ,  Min-Chuan Tsai ,  Chien-Hao Chen ,  Wei-Yu Chen ,  Chin-Fu Lin ,  JING-GANG LI ,  Min-Hsien Chen ,  JIAN-HONG SU

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L21/76846 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/2855 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53223 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for filling a trench with a metal layer is disclosed. A deposition apparatus having a plurality of supporting pins is provided. A substrate and a dielectric layer disposed thereon are provided. The dielectric layer has a trench. A first deposition process is performed immediately after the substrate is placed on the supporting pins to form a metal layer in the trench, wherein during the first deposition process a temperature of the substrate is gradually increased to reach a predetermined temperature. When the temperature of the substrate reaches the predetermined temperature, a second deposition process is performed to completely fill the trench with the metal layer. The present invention further provides a semiconductor device having an aluminum layer with a reflectivity greater than 1, wherein the semiconductor device is formed by using the method.

Abstract translation: 公开了一种用金属层填充沟槽的方法。 提供具有多个支撑销的沉积装置。 设置有基板和介电层。 电介质层具有沟槽。 在将衬底放置在支撑销上以在沟槽中形成金属层之后立即执行第一沉积工艺，其中在第一沉积工艺期间，衬底的温度逐渐增加以达到预定温度。 当基板的温度达到预定温度时，执行第二沉积工艺以用金属层完全填充沟槽。 本发明还提供了具有大于1的反射率的铝层的半导体器件，其中通过使用该方法形成半导体器件。

公开(公告)号：US20160276157A1

公开(公告)日：2016-09-22

申请号：US15169472

申请日：2016-05-31

Applicant: United Microelectronics Corp.

Inventor： Chun-Hsien Lin ,  Min-Hsien Chen

IPC: H01L21/28 ,  H01L29/66 ,  H01L21/285

CPC classification number: H01L21/28088 ,  H01L21/2855 ,  H01L21/823842 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66636

Abstract: A method of forming a semiconductor device is disclosed. A substrate having a dielectric layer thereon is provided. The dielectric layer has a gate trench therein and a gate dielectric layer is formed on a bottom of the gate trench. A work function metal layer and a top barrier layer are sequentially formed in the gate trench. A treatment is performed to the top barrier layer so as to form a silicon-containing top barrier layer. A low-resistivity metal layer is formed in the gate trench.

Abstract translation: 公开了一种形成半导体器件的方法。 提供其上具有介电层的基板。 电介质层在其中具有栅极沟槽，栅极电介质层形成在栅极沟槽的底部。 工作功能金属层和顶部阻挡层依次形成在栅极沟槽中。 对顶部阻挡层进行处理以形成含硅顶部阻挡层。 在栅极沟槽中形成低电阻率金属层。

公开(公告)号：US09558996B2

公开(公告)日：2017-01-31

申请号：US14480648

申请日：2014-09-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chi-Mao Hsu ,  Hsin-Fu Huang ,  Min-Chuan Tsai ,  Chien-Hao Chen ,  Wei-Yu Chen ,  Chin-Fu Lin ,  Jing-Gang Li ,  Min-Hsien Chen ,  Jian-Hong Su

IPC: H01L21/768 ,  H01L21/285 ,  H01L21/28 ,  H01L29/66 ,  H01L23/522 ,  H01L23/532 ,  H01L29/51

CPC classification number: H01L21/76846 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/2855 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53223 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for filling a trench with a metal layer is disclosed. A deposition apparatus having a plurality of supporting pins is provided. A substrate and a dielectric layer disposed thereon are provided. The dielectric layer has a trench. A first deposition process is performed immediately after the substrate is placed on the supporting pins to form a metal layer in the trench, wherein during the first deposition process a temperature of the substrate is gradually increased to reach a predetermined temperature. When the temperature of the substrate reaches the predetermined temperature, a second deposition process is performed to completely fill the trench with the metal layer. The present invention further provides a semiconductor device having an aluminum layer with a reflectivity greater than 1, wherein the semiconductor device is formed by using the method.

Abstract translation: 公开了一种用金属层填充沟槽的方法。 提供具有多个支撑销的沉积装置。 设置有基板和介电层。 电介质层具有沟槽。 在将基板放置在支撑销上以在沟槽中形成金属层之后立即执行第一沉积工艺，其中在第一沉积工艺期间，基板的温度逐渐增加以达到预定温度。 当基板的温度达到预定温度时，执行第二沉积工艺以用金属层完全填充沟槽。 本发明还提供了具有大于1的反射率的铝层的半导体器件，其中通过使用该方法形成半导体器件。