公开(公告)号：US10672860B2

公开(公告)日：2020-06-02

申请号：US16587305

申请日：2019-09-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Chung Hsu ,  Chung-Long Chang ,  Tsung-Yu Yang ,  Hung-Chi Li ,  Cheng-Chieh Hsieh ,  Che-Yung Lin ,  Grace Chang

IPC: H01L49/02 ,  H01F27/28 ,  H01L23/00 ,  H01F27/29 ,  H01F27/24 ,  H01L21/768 ,  H05K1/18 ,  H01L23/528 ,  H01L23/522 ,  H01L21/321 ,  H01L21/027

Abstract: A multi-terminal inductor and method for forming the multi-terminal inductor are provided. In some embodiments, an interconnect structure is arranged over a semiconductor substrate. A passivation layer is arranged over the interconnect structure. A first magnetic layer is arranged over the passivation layer, and a conductive wire laterally extends from a first input/output (I/O) bond structure at a first location to a second I/O bond structure at a second location. A third I/O bond structure branches off of the conductive wire at a third location between the first location and the second location. A connection between the third I/O bond structure and the first I/O bond structure has a first inductance. Alternatively, a connection between the first I/O bond structure and the second I/O bond structure has a second inductance different than the first inductance.

公开(公告)号：US20200286981A1

公开(公告)日：2020-09-10

申请号：US16879913

申请日：2020-05-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Chung Hsu ,  Chung-Long Chang ,  Tsung-Yu Yang ,  Hung-Chi Li ,  Cheng-Chieh Hsieh ,  Che-Yung Lin ,  Grace Chang

IPC: H01L49/02 ,  H01L23/00 ,  H01F27/28 ,  H01F27/24 ,  H01F27/29 ,  H05K1/18 ,  H01L23/528 ,  H01L21/768 ,  H01L23/522

Abstract: A multi-terminal inductor and method for forming the multi-terminal inductor are provided. In some embodiments, an interconnect structure is arranged over a semiconductor substrate. A passivation layer is arranged over the interconnect structure. A first magnetic layer is arranged over the passivation layer, and a conductive wire laterally extends from a first input/output (I/O) bond structure at a first location to a second I/O bond structure at a second location. A third I/O bond structure branches off of the conductive wire at a third location between the first location and the second location. A connection between the third I/O bond structure and the first I/O bond structure has a first inductance. Alternatively, a connection between the first I/O bond structure and the second I/O bond structure has a second inductance different than the first inductance.

公开(公告)号：US20200066831A1

公开(公告)日：2020-02-27

申请号：US16587305

申请日：2019-09-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Chung Hsu ,  Chung-Long Chang ,  Tsung-Yu Yang ,  Hung-Chi Li ,  Cheng-Chieh Hsieh ,  Che-Yung Lin ,  Grace Chang

IPC: H01L49/02 ,  H01L23/522 ,  H01F27/28 ,  H01L23/00 ,  H01F27/29 ,  H01F27/24 ,  H01L21/768 ,  H05K1/18 ,  H01L23/528

Abstract: A multi-terminal inductor and method for forming the multi-terminal inductor are provided. In some embodiments, an interconnect structure is arranged over a semiconductor substrate. A passivation layer is arranged over the interconnect structure. A first magnetic layer is arranged over the passivation layer, and a conductive wire laterally extends from a first input/output (I/O) bond structure at a first location to a second I/O bond structure at a second location. A third I/O bond structure branches off of the conductive wire at a third location between the first location and the second location. A connection between the third I/O bond structure and the first I/O bond structure has a first inductance. Alternatively, a connection between the first I/O bond structure and the second I/O bond structure has a second inductance different than the first inductance.

公开(公告)号：US11264378B2

公开(公告)日：2022-03-01

申请号：US16724024

申请日：2019-12-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shao-Yu Chen ,  Chih-Ping Chao ,  Chun-Hung Chen ,  Chung-Long Chang ,  Kuan-Chi Tsai ,  Wei-Kung Tsai ,  Hsiang-Chi Chen ,  Ching-Chung Hsu ,  Cheng-Chang Hsu ,  Yi-Sin Wang

IPC: H01L27/07 ,  H01L49/02 ,  H01L23/522

Abstract: A device includes a dielectric layer, an interlayer metal pad in the dielectric layer, a first capacitor over the interlayer metal pad, and a second capacitor over the dielectric layer. The first capacitor includes a first bottom capacitor electrode over and in contact with the interlayer metal pad, a first top capacitor electrode, and a first inter-electrode dielectric layer between the first bottom capacitor electrode and the first top capacitor electrode. The second capacitor includes a second bottom capacitor electrode over and in contact with the dielectric layer, a second top capacitor electrode, and a second inter-electrode dielectric layer between the second bottom capacitor electrode and the second top capacitor electrode.

公开(公告)号：US10515949B2

公开(公告)日：2019-12-24

申请号：US14056725

申请日：2013-10-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shao-Yu Chen ,  Chih-Ping Chao ,  Chun-Hung Chen ,  Chung-Long Chang ,  Kuan-Chi Tsai ,  Wei-Kung Tsai ,  Hsiang-Chi Chen ,  Ching-Chung Hsu ,  Cheng-Chang Hsu ,  Yi-Sin Wang

IPC: H01L27/07 ,  H01L49/02

Abstract: An integrated circuit includes a stacked MIM capacitor and a thin film resistor and methods of fabricating the same are disclosed. A capacitor bottom metal in one capacitor of the stacked MIM capacitor and the thin film resistor are substantially at the same layer of the integrated circuit, and the capacitor bottom metal and the thin film resistor are also made of substantially the same materials. The integrated circuit with both of a stacked MIM capacitor and a thin film resistor can be made in a cost benefit way accordingly, so as to overcome disadvantages mentioned above.

公开(公告)号：US10475877B1

公开(公告)日：2019-11-12

申请号：US16106525

申请日：2018-08-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Chung Hsu ,  Chung-Long Chang ,  Tsung-Yu Yang ,  Hung-Chi Li ,  Cheng-Chieh Hsieh ,  Che-Yung Lin ,  Grace Chang

IPC: H01L49/02 ,  H01L23/00 ,  H01F27/28 ,  H01F27/24 ,  H01F27/29 ,  H05K1/18 ,  H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L21/321 ,  H01L21/027

Abstract: A multi-terminal inductor and method for forming the multi-terminal inductor are provided. In some embodiments, an interconnect structure is arranged over a semiconductor substrate. A passivation layer is arranged over the interconnect structure. A first magnetic layer is arranged over the passivation layer, and a conductive wire laterally extends from a first input/output (I/O) bond structure at a first location to a second I/O bond structure at a second location. A third I/O bond structure branches off of the conductive wire at a third location between the first location and the second location. A connection between the third I/O bond structure and the first I/O bond structure has a first inductance. Alternatively, a connection between the first I/O bond structure and the second I/O bond structure has a second inductance different than the first inductance.

公开(公告)号：US09269591B2

公开(公告)日：2016-02-23

申请号：US14222785

申请日：2014-03-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Alex Kalnitsky ,  Chung-Long Chang ,  Yung-Chih Tsai ,  Tsung-Yu Yang ,  Keng-Yu Chen ,  Yong-En Syu

IPC: H01L21/322 ,  H01L27/12 ,  H01L29/34

CPC classification number: H01L21/3226 ,  H01L21/26506 ,  H01L21/304 ,  H01L21/3046 ,  H01L21/32105 ,  H01L21/7624 ,  H01L27/1203 ,  H01L29/34

Abstract: The present disclosure relates to a silicon-on-insulator (SOI) substrate having a trap-rich layer, with crystal defects, which is disposed within a handle wafer, and an associated method of formation. In some embodiments, the SOI substrate has a handle wafer. A trap-rich layer, having a plurality of crystal defects that act to trap carriers, is disposed within the handle wafer at a position abutting a top surface of the handle wafer. An insulating layer is disposed onto the handle wafer. The insulating layer has a first side abutting the top surface of the handle wafer and an opposing second side abutting a thin layer of active silicon. By forming the trap-rich layer within the handle wafer, fabrication costs associated with depositing a trap-rich material (e.g., polysilicon) onto a handle wafer are reduced and thermal instability issues are prevented.

Abstract translation: 本公开内容涉及具有富集陷阱层的绝缘体上硅（SOI）衬底，其具有设置在处理晶片内的晶体缺陷以及相关联的形成方法。 在一些实施例中，SOI衬底具有处理晶片。 在与处理晶片的顶表面相邻的位置处，在处理晶片内设置具有多个用于捕获载流子的晶体缺陷的富含阱的层。 绝缘层设置在手柄晶片上。 绝缘层具有邻接手柄晶片的顶表面的第一侧和与活性硅薄层邻接的相对的第二侧。 通过在处理晶片内形成富含阱的层，减少了将富含陷阱的材料（例如多晶硅）沉积到处理晶片上的制造成本，并防止了热不稳定性问题。

公开(公告)号：US20150108607A1

公开(公告)日：2015-04-23

申请号：US14056725

申请日：2013-10-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shao-Yu CHEN ,  Chih-Ping Chao ,  Chun-Hung Chen ,  Chung-Long Chang ,  Kuan-Chi Tsai ,  Wei-Kung Tsai ,  Hsiang-Chi Chen ,  Ching-Chung Hsu ,  Cheng-Chang Hsu ,  Yi-Sin Wang

IPC: H01L27/07 ,  H01L23/538 ,  H01L49/02

Abstract: An integrated circuit includes a stacked MIM capacitor and a thin film resistor and methods of fabricating the same are disclosed. A capacitor bottom metal in one capacitor of the stacked MIM capacitor and the thin film resistor are substantially at the same layer of the integrated circuit, and the capacitor bottom metal and the thin film resistor are also made of substantially the same materials. The integrated circuit with both of a stacked MIM capacitor and a thin film resistor can be made in a cost benefit way accordingly, so as to overcome disadvantages mentioned above.

Abstract translation: 一种集成电路包括堆叠的MIM电容器和薄膜电阻器及其制造方法。 堆叠的MIM电容器的一个电容器中的电容器底部金属和薄膜电阻器基本上处于集成电路的相同层，并且电容器底部金属和薄膜电阻器也由基本上相同的材料制成。 具有层叠MIM电容器和薄膜电阻器的集成电路可以相应地以成本有益的方式制造，以克服上述缺点。

公开(公告)号：US10090327B2

公开(公告)日：2018-10-02

申请号：US14158430

申请日：2014-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Yu Cheng ,  Keng-Yu Chen ,  Wei-Kung Tsai ,  Kuan-Chi Tsai ,  Tsung-Yu Yang ,  Chung-Long Chang ,  Chun-Hung Chen ,  Chih-Ping Chao

IPC: H01L27/12 ,  H01L27/06 ,  H01L21/306 ,  H01L21/311 ,  H01L21/28 ,  H01L23/66 ,  H01L21/762 ,  H01L21/02 ,  H01L49/02 ,  H01L21/84 ,  H01L21/763 ,  H01L23/522

Abstract: Embodiments for forming a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a buried oxide layer formed over the substrate. An interface layer is formed between the substrate and the buried oxide layer. The semiconductor device structure also includes a silicon layer formed over the buried oxide layer; and a polysilicon layer formed over the substrate and in a deep trench. The polysilicon layer extends through the silicon layer, the buried oxide layer and the interface layer.

公开(公告)号：US09589831B2

公开(公告)日：2017-03-07

申请号：US14971031

申请日：2015-12-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Kuo-Yu Cheng ,  Keng-Yu Chen ,  Wei-Kung Tsai ,  Kuan-Chi Tsai ,  Tsung-Yu Yang ,  Chung-Long Chang ,  Chun-Hung Chen ,  Chih-Ping Chao

IPC: H01L27/12 ,  H01L21/306 ,  H01L21/762 ,  H01L21/84

CPC classification number: H01L21/76283 ,  H01L21/7624 ,  H01L21/84 ,  H01L27/1203

Abstract: A method for forming a radio frequency area of an integrated circuit are provided. The method includes forming a buried oxide layer over a substrate, and an interface layer is formed between the substrate and the buried oxide layer. The method also includes etching through the buried oxide layer and the interface layer to form a deep trench, and a bottom surface of the deep trench is level with a bottom surface of the interface layer. The method further includes forming an implant region directly below the deep trench and forming an interlayer dielectric layer in the deep trench.

Abstract translation: 提供了一种用于形成集成电路的射频区域的方法。 该方法包括在衬底上形成掩埋氧化物层，并且在衬底和掩埋氧化物层之间形成界面层。 该方法还包括通过掩埋氧化物层和界面层蚀刻以形成深沟槽，并且深沟槽的底表面与界面层的底表面平齐。 该方法还包括在深沟槽的正下方形成植入区域，并在深沟槽中形成层间电介质层。