公开(公告)号：US11435660B2

公开(公告)日：2022-09-06

申请号：US15967159

申请日：2018-04-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsin-Chang Lee ,  Ping-Hsun Lin ,  Yen-Cheng Ho ,  Chih-Cheng Lin ,  Chia-Jen Chen

IPC: G03F1/24 ,  G03F1/52 ,  G03F1/68 ,  G03F1/54 ,  G03F1/26

Abstract: A method of fabricating a photomask includes selectively exposing portions of a photomask blank to radiation to change an optical property of the portions of the photomask blank exposed to the radiation, thereby forming a pattern of exposed portions of the photomask blank and unexposed portions of the photomask blank. The pattern corresponds to a pattern of semiconductor device features.

公开(公告)号：US11038029B2

公开(公告)日：2021-06-15

申请号：US16277262

申请日：2019-02-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsueh-Wen Tsau ,  Chun-I Wu ,  Ziwei Fang ,  Huang-Lin Chao ,  I-Ming Chang ,  Chung-Liang Cheng ,  Chih-Cheng Lin

IPC: H01L29/40 ,  H01L29/78 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L29/423 ,  H01L29/49 ,  H01L21/28 ,  H01L29/66 ,  H01L21/285 ,  H01L29/06

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate and an insulating layer over the substrate. The insulating layer has a trench partially exposing the substrate. The method includes forming a gate dielectric layer in the trench. The method includes forming a first metal-containing layer over the gate dielectric layer. The method includes forming a silicon-containing layer over the first metal-containing layer. The method includes forming a second metal-containing layer over the silicon-containing layer. The method includes forming a gate electrode layer in the trench and over the second metal-containing layer.

公开(公告)号：US10747103B2

公开(公告)日：2020-08-18

申请号：US16228339

申请日：2018-12-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun-Yue Lin ,  Hsuan-Chen Chen ,  Chih-Cheng Lin ,  Hsin-Chang Lee ,  Yao-Ching Ku ,  Wei-Jen Lo ,  Anthony Yen ,  Chin-Hsiang Lin ,  Mark Chien

IPC: G03F1/62 ,  G03F1/24

Abstract: A method for fabricating a pellicle includes forming a first dielectric layer over a back surface of a substrate. After forming the first dielectric layer, and in some embodiments, a graphene layer is formed over a front surface of the substrate. In some examples, after forming the graphene layer, the first dielectric layer is patterned to form an opening in the first dielectric layer that exposes a portion of the back surface of the substrate. Thereafter, while using the patterned first dielectric layer as a mask, an etching process may be performed to the back surface of the substrate to form a pellicle having a pellicle membrane that includes the graphene layer.

公开(公告)号：US20180149959A1

公开(公告)日：2018-05-31

申请号：US15670183

申请日：2017-08-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun-Yue Lin ,  Hsin-Chang Lee ,  Chia-Jen Chen ,  Chih-Cheng Lin ,  Anthony Yen ,  Chin-Hsiang Lin

IPC: G03F1/24 ,  G03F1/54 ,  G03F1/42 ,  G03F1/26 ,  G03F1/48

CPC classification number: G03F1/24 ,  G03F1/26 ,  G03F1/42 ,  G03F1/48 ,  G03F1/50 ,  G03F1/54

Abstract: A lithography mask includes a substrate that contains a low thermal expansion material (LTEM). A reflective structure is disposed over a first side of the substrate. An absorber layer is disposed over the reflective structure. The absorber layer contains one or more first overlay marks. A conductive layer is disposed over a second side of the substrate, the second side being opposite the first side. The conductive layer contains portions of one or more second overlay marks. In some embodiments, the lithography mask includes an EUV lithography mask.

公开(公告)号：US20180059534A1

公开(公告)日：2018-03-01

申请号：US15356204

申请日：2016-11-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chiang Tu ,  Chun-Lang Chen ,  Chue San Yoo ,  Jong-Yuh Chang ,  Chia-Shiung Tsai ,  Ping-Yin Liu ,  Hsin-Chang Lee ,  Chih-Cheng Lin ,  Yun-Yue Lin

IPC: G03F1/62 ,  H01L21/033

CPC classification number: G03F1/62 ,  C23C14/16 ,  C23C14/165 ,  C23C14/18 ,  C23C16/01 ,  C23C16/26 ,  C23C16/56 ,  C23C28/32 ,  G03F1/64 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337

Abstract: A method includes depositing a first material layer over a first substrate; and depositing a graphene layer over the first material layer. The method further includes depositing an amorphous silicon layer over the graphene layer and bonding the amorphous silicon layer to a second substrate, thereby forming an assembly. The method further includes annealing the assembly, thereby converting the amorphous silicon layer to a silicon oxide layer. The method further includes removing the first substrate from the assembly and removing the first material layer from the assembly, thereby exposing the graphene layer.

公开(公告)号：US11137684B2

公开(公告)日：2021-10-05

申请号：US16719118

申请日：2019-12-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun-Yue Lin ,  Hsin-Chang Lee ,  Chia-Jen Chen ,  Chih-Cheng Lin ,  Anthony Yen ,  Chin-Hsiang Lin

IPC: G03F7/20 ,  G03F1/50 ,  G03F1/24 ,  G03F1/26 ,  G03F1/42 ,  G03F1/48 ,  G03F1/54

Abstract: A method of performing a lithography process includes receiving a lithography mask and performing overlay measurement. The lithography mask includes a substrate that contains a low thermal expansion material (LTEM); a reflective structure over a first side of the substrate; an absorber layer over the reflective structure and containing one or more first overlay marks; and a conductive layer over a second side of the substrate and containing one or more second overlay marks. The second side is opposite the first side. The overlay measurement includes using the one or more first overlay marks in an extreme ultraviolet (EUV) lithography process or using the one or more second overlay marks in a non-EUV lithography process.

公开(公告)号：US10162258B2

公开(公告)日：2018-12-25

申请号：US15381033

申请日：2016-12-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun-Yue Lin ,  Hsuan-Chen Chen ,  Chih-Cheng Lin ,  Hsin-Chang Lee ,  Yao-Ching Ku ,  Wei-Jen Lo ,  Anthony Yen ,  Chin-Hsiang Lin ,  Mark Chien

IPC: G03F1/24 ,  G03F1/62

Abstract: A method for fabricating a pellicle includes forming a first dielectric layer over a back surface of a substrate. After forming the first dielectric layer, and in some embodiments, a graphene layer is formed over a front surface of the substrate. In some examples, after forming the graphene layer, the first dielectric layer is patterned to form an opening in the first dielectric layer that exposes a portion of the back surface of the substrate. Thereafter, while using the patterned first dielectric layer as a mask, an etching process may be performed to the back surface of the substrate to form a pellicle having a pellicle membrane that includes the graphene layer.

公开(公告)号：US10012899B2

公开(公告)日：2018-07-03

申请号：US15356204

申请日：2016-11-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chiang Tu ,  Chun-Lang Chen ,  Chue San Yoo ,  Jong-Yuh Chang ,  Chia-Shiung Tsai ,  Ping-Yin Liu ,  Hsin-Chang Lee ,  Chih-Cheng Lin ,  Yun-Yue Lin

IPC: G03F1/62 ,  G03F1/64 ,  H01L21/033 ,  C23C14/16 ,  C23C16/26 ,  C23C28/00 ,  C23C14/18

CPC classification number: G03F1/62 ,  C23C14/16 ,  C23C14/165 ,  C23C14/18 ,  C23C16/01 ,  C23C16/26 ,  C23C16/56 ,  C23C28/32 ,  G03F1/64 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337

Abstract: A method includes depositing a first material layer over a first substrate; and depositing a graphene layer over the first material layer. The method further includes depositing an amorphous silicon layer over the graphene layer and bonding the amorphous silicon layer to a second substrate, thereby forming an assembly. The method further includes annealing the assembly, thereby converting the amorphous silicon layer to a silicon oxide layer. The method further includes removing the first substrate from the assembly and removing the first material layer from the assembly, thereby exposing the graphene layer.

公开(公告)号：US11018022B2

公开(公告)日：2021-05-25

申请号：US16035159

申请日：2018-07-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Ming Chang ,  Chih-Cheng Lin ,  Chi-Ying Wu ,  Wei-Ming You ,  Ziwei Fang ,  Huang-Lin Chao

IPC: H01L21/335 ,  H01L21/8232 ,  H01L21/425 ,  H01L21/322 ,  H01L21/28 ,  H01L29/78 ,  H01L21/762 ,  H01L29/165 ,  H01L29/66

Abstract: A method for forming a semiconductor device structure is provided. The method includes depositing a gate dielectric layer over a substrate. The substrate has a base portion and a first fin portion over the base portion, and the gate dielectric layer is over the first fin portion. The method includes forming a gate electrode layer over the gate dielectric layer. The gate electrode layer includes fluorine. The method includes annealing the gate electrode layer and the gate dielectric layer so that fluorine from the gate electrode layer diffuses into the gate dielectric layer.

公开(公告)号：US10514597B2

公开(公告)日：2019-12-24

申请号：US15670183

申请日：2017-08-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun-Yue Lin ,  Hsin-Chang Lee ,  Chia-Jen Chen ,  Chih-Cheng Lin ,  Anthony Yen ,  Chin-Hsiang Lin

IPC: G03F1/24 ,  G03F1/26 ,  G03F1/42 ,  G03F1/48 ,  G03F1/54 ,  G03F1/50

Abstract: A lithography mask includes a substrate that contains a low thermal expansion material (LTEM). A reflective structure is disposed over a first side of the substrate. An absorber layer is disposed over the reflective structure. The absorber layer contains one or more first overlay marks. A conductive layer is disposed over a second side of the substrate, the second side being opposite the first side. The conductive layer contains portions of one or more second overlay marks. In some embodiments, the lithography mask includes an EUV lithography mask.