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公开(公告)号：US20220208237A1
公开(公告)日：2022-06-30
申请号：US17407585
申请日：2021-08-20
Applicant: Samsung Electronics Co., Ltd.
Inventor： Chang Min LEE , Nam Hyung KIM , Dae Jeong KIM , Do Han KIM , Min Su KIM , Deok Ho SEO , Won Jae SHIN , Yong Jun YU , Il Gyu JUNG , In Su CHOI
Abstract: An electronic device including a memory device with improved reliability is provided. The semiconductor device comprises a data pin configured to transmit a data signal, a command/address pin configured to transmit a command and an address, a command/address receiver connected to the command/address pin, and a computing unit connected to the command/address receiver, wherein the command/address receiver receives a first command and a first address from the outside through the command/address pin and generates a first instruction on the basis of the first command and the first address, and the computing unit receives the first instruction and performs computation based on the first instruction.
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公开(公告)号：US20220215866A1
公开(公告)日：2022-07-07
申请号：US17480359
申请日：2021-09-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yong Jun YU , Nam Hyung KIM , Do-Han KIM , Min Su KIM , Deok Ho SEO , Won Jae SHIN , Chang Min LEE , Il Gyu JUNG , In Su CHOI
Abstract: A semiconductor device including a memory device which has improved reliability is provided. The semiconductor device comprises at least one data pin configured to transfer a data signal, at least one command address pin configured to transfer a command and an address, at least one serial pin configured to transfer a serial data signal, and processing circuitry connected to the at least one data pin and the at least one serial pin. The processing circuitry is configured to receive the data signal from outside through the at least one data pin, and the processing circuitry is configured to output the serial data signal through the at least one serial pin in response to the received data signal.
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公开(公告)号：US20180351763A1
公开(公告)日：2018-12-06
申请号：US15778801
申请日：2016-11-24
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyun-Woo OCK , Sung Bin IM , Young Min KO , Hyun Joong KIM , Hyun Jin OH , Young Seon KONG , Min Su KIM , Seok Min BAE , Suk Tae CHOI , Jung Mo YEON , Lye Suk LEE
Abstract: A smart home service which is capable of providing an environment in which calling a control command for a device is available via a user terminal protocol to control between the device and a user terminal based on different type of protocol and a control method for the same. The smart home service server connecting at least one device operated based on a first protocol to at least one user terminal operated based on a second protocol, includes an application programming interface (API) controller configured to allow a control command for the at least one device to be called via the second protocol of the at least one user terminal; a filter configured to convert the called control command according to the first protocol; and a control command transmitter configured to transmit the control command converted according to the first protocol, to the at least one device.
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公开(公告)号：US20170222630A1
公开(公告)日：2017-08-03
申请号：US15417339
申请日：2017-01-27
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jong Woo KIM , Ju Hyun KANG , Min Su KIM , Ka Ram LEE
IPC: H03K3/012 , H03K3/3562
CPC classification number: H03K3/012 , H03K3/35625
Abstract: A semiconductor device may include a master latch that stores an input data signal, using a local power supply voltage and a clock signal, and outputs the input data signal to a first output signal; a slave latch that stores the first output signal, using a global power supply voltage, the clock signal and a retention signal, and outputs a second output signal; a first logic gate that receives input of one signal and another signal of the retention signal, the clock signal and the reset signal, and outputs a first control signal generated by performing a first logical operation; and a second logic gate that receives input of the rest of the retention signal, the clock signal and the reset signal, and the first control signal, and performs a second logical operation to at least one of the master latch and the slave latch.
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公开(公告)号：US20160242256A1
公开(公告)日：2016-08-18
申请号：US15139701
申请日：2016-04-27
Applicant: Samsung Electronics Co., ltd.
Inventor： Chang Seob KIM , Min Su KIM
CPC classification number: H05B33/0872 , H05B33/0854 , H05B37/0218 , H05B37/0254 , H05B37/0272
Abstract: A lighting system includes a digital addressable lighting interface (DALI) master controller, a lighting driver, and a signal converter. The DALI master controller is connected to a management server. The lighting driver operates a lighting device including a light emitting diode (LED). The signal converter is connected to the DALI master controller by a DALI bus operating according to a DALI communication protocol, and is communicatively connected to the lighting driver via a wireless communication connection operating according to a wireless communication protocol. The signal converter inter-converts a signal transmitted and received from the DALI master controller according to the DALI communication protocol and a signal transmitted to and received from the lighting driver according to the wireless communication protocol so as to enable communication between the lighting driver and the DALI master controller.
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Patent Agency Ranking
公开(公告)号：US20150130365A1
公开(公告)日：2015-05-14
申请号：US14460313
申请日：2014-08-14
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Chang Seob KIM , Min Su KIM
CPC classification number: H05B33/0872 , H05B33/0854 , H05B37/0218 , H05B37/0254 , H05B37/0272
Abstract: A lighting system includes a digital addressable lighting interface (DALI) master controller, a lighting driver, and a signal converter. The DALI master controller is connected to a management server. The lighting driver operates a lighting device including a light emitting diode (LED). The signal converter is connected to the DALI master controller by a DALI bus operating according to a DALI communication protocol, and is communicatively connected to the lighting driver via a wireless communication connection operating according to a wireless communication protocol. The signal converter inter-converts a signal transmitted and received from the DALI master controller according to the DALI communication protocol and a signal transmitted to and received from the lighting driver according to the wireless communication protocol so as to enable communication between the lighting driver and the DALI master controller.
Abstract translation: 照明系统包括数字可寻址照明接口（DALI）主控制器，照明驱动器和信号转换器。 DALI主控制器连接到管理服务器。 照明驱动器操作包括发光二极管（LED）的照明装置。 信号转换器通过根据DALI通信协议操作的DALI总线连接到DALI主控制器，并且通过根据无线通信协议操作的无线通信连接通信地连接到照明驱动器。 信号转换器根据DALI通信协议将从DALI主控制器发送和接收的信号和根据无线通信协议发送到照明驱动器的信号和从照明驱动器接收的信号相互转换，以使得照明驱动器和 DALI主控制器。
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公开(公告)号：US20130257480A1
公开(公告)日：2013-10-03
申请号：US13725208
申请日：2012-12-21
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Min Su KIM
IPC: H03K19/096
CPC classification number: H03K19/0963 , H03K19/096 , H03K19/0966
Abstract: A clock-delayed domino logic circuit includes a precharge circuit configured to control connection between a first node and a dynamic node in response to a clock signal, an evaluation circuit configured to control connection between a second node and an evaluation node in response to the clock signal, a logic network connected between the dynamic node and the evaluation node, the logic network configured to determine a logic level of the dynamic node based on a plurality of input signals, and a phase control circuit configured to output a logic level of the evaluation node or a logic level of the first node according to a level of the clock signal.
Abstract translation: 时钟延迟的多米诺骨牌逻辑电路包括预充电电路，其被配置为响应于时钟信号来控制第一节点和动态节点之间的连接，评估电路被配置为响应于时钟来控制第二节点和评估节点之间的连接 信号，连接在所述动态节点和所述评估节点之间的逻辑网络，所述逻辑网络被配置为基于多个输入信号来确定所述动态节点的逻辑电平;以及相位控制电路，被配置为输出所述评估的逻辑电平 节点或第一节点的逻辑电平。
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公开(公告)号：US20220149821A1
公开(公告)日：2022-05-12
申请号：US17385182
申请日：2021-07-26
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyun Chul HWANG , Min Su KIM
IPC: H03K3/037
Abstract: A semiconductor circuit may include a first flip-flop configured to output a first input data as a first output signal in response to an inverted input clock signal, a second flip-flop configured to output a second input data as a second output signal in response to an input clock signal, a glitch-free circuit configured to receive the inverted input clock signal, the input clock signal, the first output signal, and the second output signal, and to determine a voltage level of a node on the basis of the inverted input clock signal, the input clock signal, the first output signal, and the second output signal, and an inverter configured to output an output clock signal obtained by inverting the voltage level of the node determined by the glitch-free circuit. The glitch-free circuit does not include a transistor having a gate connected to the node.
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公开(公告)号：US20210119617A1
公开(公告)日：2021-04-22
申请号：US16866941
申请日：2020-05-05
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyun LEE , Min Su KIM , Ah Reum KIM
IPC: H03K3/3562 , H01L23/528 , H01L27/02
Abstract: A semiconductor device is provided. The semiconductor device includes a clock gate line supplying a clock signal, an inverted clock gate line disposed in parallel to the clock gate line and supplying an inverted clock signal, a first latch circuit performing a first latch operation based on the clock signal and the inverted clock signal and a second latch circuit disposed on a side of the first latch circuit in a first direction, receiving an output of the first latch circuit, and operating based on the clock signal and the inverted clock, wherein the clock gate line and the inverted clock gate line extend in the first direction and are shared by the first and second latch circuits.
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公开(公告)号：US20180350815A1
公开(公告)日：2018-12-06
申请号：US16059562
申请日：2018-08-09
Applicant: Samsung Electronics Co., Ltd.
Inventor： Dae Seong LEE , Min Su KIM
IPC: H01L27/092 , H01L29/78 , H03K19/0948 , H03K19/20 , H01L23/528 , H03K3/356 , H03K3/3562
CPC classification number: H01L27/0924 , H01L21/823828 , H01L21/823871 , H01L23/528 , H01L27/0207 , H01L27/092 , H01L29/785 , H03K3/356156 , H03K3/35625 , H03K19/0948 , H03K19/20
Abstract: A semiconductor device includes a first active region, a second active region, a first gate line disposed to overlap the first and second active regions, a second gate line disposed to overlap the first and second active regions, a first metal line electrically connecting the first and second gate lines and providing a first signal to both the first and second gate lines, a first contact structure electrically connected to part of the first active region between the first and second gate lines, a second contact structure electrically connected to part of the second active region between the first and second gate lines, and a second metal line electrically connected to the first and second contact structures and transmitting a second signal, wherein an overlapped region that is overlapped by the second metal line does not include a break region.
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