公开(公告)号：US20180331046A1

公开(公告)日：2018-11-15

申请号：US16026937

申请日：2018-07-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiseok LEE ,  Sooho SHIN ,  Juik LEE ,  Jun Ho LEE ,  Kwangmin KIM ,  Ilyoung MOON ,  Jemin PARK ,  Bumseok SEO ,  Chan-Sic YOON ,  Hoin LEE

IPC: H01L23/544 ,  H01L27/108

CPC classification number: H01L23/544 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10894 ,  H01L27/10897 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/5446

Abstract: A semiconductor device includes an alignment key on a substrate. The alignment key includes a first sub-alignment key pattern with a first conductive pattern, a second conductive pattern, and a capping dielectric pattern that are sequentially stacked on the substrate, an alignment key trench that penetrates at least a portion of the first sub-alignment key pattern, and a lower conductive pattern in the alignment key trench. The alignment key trench includes an upper trench that is provided in the capping dielectric pattern that has a first width, and a lower trench that extends downward from the upper trench and that has a second width less than the first width. The lower conductive pattern includes sidewall conductive patterns that are separately disposed on opposite sidewalls of the lower trench.

公开(公告)号：US20170200616A1

公开(公告)日：2017-07-13

申请号：US15377113

申请日：2016-12-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyo-sun MIN ,  Yoonjae KIM ,  Sooho SHIN ,  Sunghee HAN

IPC: H01L21/306 ,  H01L21/822 ,  H01L21/265 ,  H01L21/768 ,  H01L21/283 ,  H01L21/308

CPC classification number: H01L21/30604 ,  H01L21/0337 ,  H01L21/26506 ,  H01L21/283 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/32139 ,  H01L21/76895 ,  H01L21/8221 ,  H01L27/10823 ,  H01L27/10894

Abstract: A method of fabricating a semiconductor device includes sequentially forming a first insulation pattern and an etch stop pattern on a peripheral circuit area of a substrate, forming a first mask pattern on a cell array area of the substrate, the first mask pattern including a pair of first portions extending in parallel and a second portion covering a portion of a sidewall of the etch stop pattern and a portion of a sidewall of the first insulation pattern, forming a second insulation layer covering the etch stop pattern and the first mask pattern, partially etching the etch stop pattern and the second insulation layer to expose the second portion of the first mask pattern, and removing the second portion of the first mask pattern to divide the pair of first portions of the first mask pattern.

公开(公告)号：US20230154876A1

公开(公告)日：2023-05-18

申请号：US18093880

申请日：2023-01-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minjung CHOI ,  Sooho SHIN ,  Yeonjin LEE ,  Junghoon HAN

IPC: H01L23/00 ,  H01L21/56

CPC classification number: H01L24/05 ,  H01L21/561 ,  H01L24/13 ,  H01L24/96 ,  H01L24/73 ,  H01L2224/81801 ,  H01L2924/1304 ,  H01L2924/18162 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2224/12105

Abstract: A semiconductor device includes an interlayer insulating layer disposed on a substrate; a plurality of middle interconnections disposed in the interlayer insulating layer; a pad disposed on the interlayer insulating layer; an upper interconnection disposed on the interlayer insulating layer; a protective insulating layer covering an edge of the pad, the upper interconnection, and a horizontal gap between the pad and the upper interconnection, the protective insulating layer having an opening on the pad; and a bump disposed on the pad, the bump extending on the protective insulating layer and overlapping the upper interconnection from a top-down view. At least one of the plurality of middle interconnections from among middle interconnections vertically closest to the pad has a first vertical thickness, the pad has a second vertical thickness that is twice to 100 times the first vertical thickness, a length of the gap between the pad and the upper interconnection is 1 μm or more, and an upper surface of the protective insulating layer is planar.

公开(公告)号：US20210043591A1

公开(公告)日：2021-02-11

申请号：US16795658

申请日：2020-02-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minjung CHOI ,  Sooho SHIN ,  Yeonjin LEE ,  Junghoon HAN

IPC: H01L23/00 ,  H01L21/56

Abstract: A semiconductor device includes an interlayer insulating layer disposed on a substrate; a plurality of middle interconnections disposed in the interlayer insulating layer; a pad disposed on the interlayer insulating layer; an upper interconnection disposed on the interlayer insulating layer; a protective insulating layer covering an edge of the pad, the upper interconnection, and a horizontal gap between the pad and the upper interconnection, the protective insulating layer having an opening on the pad; and a bump disposed on the pad, the bump extending on the protective insulating layer and overlapping the upper interconnection from a top-down view. At least one of the plurality of middle interconnections from among middle interconnections vertically closest to the pad has a first vertical thickness, the pad has a second vertical thickness that is twice to 100 times the first vertical thickness, a length of the gap between the pad and the upper interconnection is 1 μm or more, and an upper surface of the protective insulating layer is planar.

公开(公告)号：US20240397706A1

公开(公告)日：2024-11-28

申请号：US18493267

申请日：2023-10-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihoon CHANG ,  Sooho SHIN

IPC: H10B12/00

Abstract: A semiconductor device including a word line intersecting and overlapping an active region and extending in a first direction, a word line capping layer on the word line, bit lines interacting and overlapping the active region and extending in a second direction, buried contacts each connected to the active region, direct contacts each connecting the active region to a corresponding one of the bit lines, a fence pattern on top of the word line capping layer, and a landing pad connected to a corresponding one of the buried contacts, wherein the fence pattern is within a fence pattern trench at a corresponding space between a corresponding pair the bit lines and between a corresponding pair the buried contacts, the fence pattern includes a first fence pattern and a second fence pattern on the first fence pattern that include different materials from each other may be provided.

公开(公告)号：US20240047390A1

公开(公告)日：2024-02-08

申请号：US18377530

申请日：2023-10-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minjung CHOI ,  Sooho SHIN ,  Yeonjin LEE ,  Junghoon HAN

IPC: H01L23/00 ,  H01L21/56

CPC classification number: H01L24/05 ,  H01L21/561 ,  H01L24/13 ,  H01L24/96 ,  H01L24/73 ,  H01L2224/81801 ,  H01L2924/1304 ,  H01L2924/18162 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2224/12105

Abstract: A semiconductor device includes an interlayer insulating layer disposed on a substrate; a plurality of middle interconnections disposed in the interlayer insulating layer; a pad disposed on the interlayer insulating layer; an upper interconnection disposed on the interlayer insulating layer; a protective insulating layer covering an edge of the pad, the upper interconnection, and a horizontal gap between the pad and the upper interconnection, the protective insulating layer having an opening on the pad; and a bump disposed on the pad, the bump extending on the protective insulating layer and overlapping the upper interconnection from a top-down view. At least one of the plurality of middle interconnections from among middle interconnections vertically closest to the pad has a first vertical thickness, the pad has a second vertical thickness that is twice to 100 times the first vertical thickness, a length of the gap between the pad and the upper interconnection is 1 μm or more, and an upper surface of the protective insulating layer is planar.

公开(公告)号：US20210280541A1

公开(公告)日：2021-09-09

申请号：US17328365

申请日：2021-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minjung CHOI ,  Sooho SHIN ,  Yeonjin LEE ,  Junghoon HAN

IPC: H01L23/00 ,  H01L21/56

Abstract: A semiconductor device includes an interlayer insulating layer disposed on a substrate; a plurality of middle interconnections disposed in the interlayer insulating layer; a pad disposed on the interlayer insulating layer; an upper interconnection disposed on the interlayer insulating layer; a protective insulating layer covering an edge of the pad, the upper interconnection, and a horizontal gap between the pad and the upper interconnection, the protective insulating layer having an opening on the pad; and a bump disposed on the pad, the bump extending on the protective insulating layer and overlapping the upper interconnection from a top-down view. At least one of the plurality of middle interconnections from among middle interconnections vertically closest to the pad has a first vertical thickness, the pad has a second vertical thickness that is twice to 100 times the first vertical thickness, a length of the gap between the pad and the upper interconnection is 1 μm or more, and an upper surface of the protective insulating layer is planar.