公开(公告)号：US20210013324A1

公开(公告)日：2021-01-14

申请号：US17038004

申请日：2020-09-30

Applicant: Samsung Electronics Co., Ltd. ,  Research & Business Foundation Sungkyunkwan University

Inventor： Jin Bum KIM ,  MunHyeon KIM ,  Hyoung Sub KIM ,  Tae Jin PARK ,  Kwan Heum LEE ,  Chang Woo NOH ,  Maria TOLEDANO LU QUE ,  Hong Bae PARK ,  Si Hyung LEE ,  Sung Man WHANG

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786

Abstract: A semiconductor device includes a substrate, a gate electrode on the substrate, a gate spacer on a sidewall of the gate electrode, an active pattern penetrating the gate electrode and the gate spacer, and an epitaxial pattern contacting the active pattern and the gate spacer. The gate electrode extends in a first direction. The gate spacer includes a semiconductor material layer. The active pattern extends in a second direction crossing the first direction.

公开(公告)号：US20200342157A1

公开(公告)日：2020-10-29

申请号：US16794045

申请日：2020-02-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Alexander SCHMIDT ,  Dong-Gwan SHIN ,  Anthony PAYET ,  Hyoung Soo KO ,  Seok Hoon KIM ,  Hyun-Kwan YU ,  Si Hyung LEE ,  In Kook JANG

IPC: G06F30/398 ,  H01L27/02 ,  G06F30/367

Abstract: A simulation method and system which can determine a predictable epitaxy time by accurately reflecting layout characteristics of a chip and characteristics of a source/drain formation process are provided. The simulation method includes storing a plurality of structure parameters of transistors for a semiconductor chip, the structure parameters determined by using imaging equipment, generating a first local layout which includes a first structure parameter extracted from a semiconductor device included in the first local layout, the first structure parameter being an actual parameter determined using the imaging equipment, generating second to n-th local layouts by modifying the first structure parameter included in the first local layout, wherein the second to n-th local layouts respectively have second to n-th structure parameters modified from the first structure parameter, calculating first to n-th effective density factors(EDF) respectively for the first to n-th structure parameters using a predetermined simulation of the first to n-th structure parameters, determining a first effective open silicon density for a first chip using the first to n-th effective density factors and a layout of the first chip, and calculating a first epitaxy time for the first effective open silicon density, calculating second to m-th epitaxy times for second to m-th effective open silicon densities, and performing a regression analysis of effective open silicon density versus epitaxy time based on the calculation result, where n is a natural number equal to or greater than 3, and m is a natural number equal to or greater than 3.

公开(公告)号：US20190198639A1

公开(公告)日：2019-06-27

申请号：US16037922

申请日：2018-07-17

Applicant: Samsung Electronics Co., Ltd. ,  Research & Business Foundation Sungkyunkwan University

Inventor： Jin Bum KIM ,  MunHyeon KIM ,  Hyoung Sub KIM ,  Tae Jin PARK ,  Kwan Heum LEE ,  Chang Woo NOH ,  Maria TOLEDANO LU QUE ,  Hong Bae PARK ,  Si Hyung LEE ,  Sung Man WHANG

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/66545 ,  H01L29/42392 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/78696

Abstract: A semiconductor device includes a substrate, a gate electrode on the substrate, a gate spacer on a sidewall of the gate electrode, an active pattern penetrating the gate electrode and the gate spacer, and an epitaxial pattern contacting the active pattern and the gate spacer. The gate electrode extends in a first direction. The gate spacer includes a semiconductor material layer. The active pattern extends in a second direction crossing the first direction.

公开(公告)号：US20230056095A1

公开(公告)日：2023-02-23

申请号：US17734564

申请日：2022-05-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Nam Kyu CHO ,  Sang Gil LEE ,  Seok Hoon KIM ,  Yong Seung KIM ,  Jung Taek KIM ,  Pan Kwi PARK ,  Dong Suk SHIN ,  Si Hyung LEE ,  Yang XU

IPC: H01L29/778 ,  H01L29/78 ,  H01L29/423

Abstract: A semiconductor device includes a substrate including a first region and a second region, a first active pattern on the first region, a first gate structure having a first width in the first direction, on the first active pattern, a first epitaxial pattern disposed in the first active pattern on a side surface of the first gate structure, a second active pattern on the second region, a second gate structure having a second width greater than the first width in the first direction, on the second active pattern and a second epitaxial pattern disposed in the second active pattern on a side surface of the second gate structure. Each of the first epitaxial pattern and the second epitaxial pattern includes silicon germanium (SiGe), and a first Ge concentration of the first epitaxial pattern is lower than a second Ge concentration of the second epitaxial pattern.

公开(公告)号：US20240332424A1

公开(公告)日：2024-10-03

申请号：US18740736

申请日：2024-06-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yang XU ,  Nam Kyu CHO ,  Seok Hoon KIM ,  Yong Seung KIM ,  Pan Kwi PARK ,  Dong Suk SHIN ,  Sang Gil LEE ,  Si Hyung LEE

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417

CPC classification number: H01L29/7851 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/41791

Abstract: A semiconductor device including first fin-shaped patterns in a first region of a substrate and spaced apart from each other in a first direction, second fin-shaped patterns in a second region of the substrate and spaced apart from each other in a second direction, a first field insulating film on the substrate and covering sidewalls of the first fin-shaped patterns, a second field insulating film on the substrate and covering sidewalls of the second fin-shaped patterns, a first source/drain pattern on the first field insulating film, connected to the first fin-shaped patterns, and including a first silicon-germanium pattern, and a second source/drain pattern on the second field insulating film, connected to the second fin-shaped patterns, and including a second silicon-germanium pattern, the second source/drain pattern and the second field insulating film defining one or more first air gaps therebetween may be provided.

公开(公告)号：US20230058991A1

公开(公告)日：2023-02-23

申请号：US17690178

申请日：2022-03-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yang XU ,  Nam Kyu CHO ,  Seok Hoon KIM ,  Yong Seung KIM ,  Pan Kwi PARK ,  Dong Suk SHIN ,  Sang Gil LEE ,  Si Hyung LEE

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/417 ,  H01L29/06

Abstract: A semiconductor device including first fin-shaped patterns in a first region of a substrate and spaced apart from each other in a first direction, second fin-shaped patterns in a second region of the substrate and spaced apart from each other in a second direction, a first field insulating film on the substrate and covering sidewalls of the first fin-shaped patterns, a second field insulating film on the substrate and covering sidewalls of the second fin-shaped patterns, a first source/drain pattern on the first field insulating film, connected to the first fin-shaped patterns, and including a first silicon-germanium pattern, and a second source/drain pattern on the second field insulating film, connected to the second fin-shaped patterns, and including a second silicon-germanium pattern, the second source/drain pattern and the second field insulating film defining one or more first air gaps therebetween may be provided.