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公开(公告)号:US10897259B1
公开(公告)日:2021-01-19
申请号:US16853076
申请日:2020-04-20
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Shinwoong Kim , Myounggyun Kim , Chulho Kim , Inhyo Ryu , Jaewon Choi , Sangwook Han , Honggul Han
Abstract: A phase locked circuit includes an oscillator configured to generate an output clock signal, a first phase detector configured to detect a phase difference between an input clock signal and a feedback clock signal based on the output clock signal, a second phase detector having a wider phase locking range than that of the first phase detector and configured to detect the phase difference between the input clock signal and the feedback clock signal, and a charge pump controller configured to control an output current of a charge pump included in the second phase detector based on the phase difference detected by the first phase detector. When the phase difference between the input clock signal and the feedback clock signal is within the phase locking range of the first phase detector, the oscillator and the first phase detector are connected to each other.
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公开(公告)号:US10917098B2
公开(公告)日:2021-02-09
申请号:US16704486
申请日:2019-12-05
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jaehyuk Jang , Sangwook Han , Shinwoong Kim , Jaeyoung Kim , Chulho Kim
Abstract: A device for wireless communication using a plurality of antennas including a first local oscillation generator configured to generate a first local oscillation signal for up-converting a first transmission signal, a second local oscillation generator configured to generate a second local oscillation signal for up-converting a second transmission signal, and a phase difference detector configured to, detect a first phase difference between the first local oscillation signal and the second local oscillation signal, and generate a first phase compensation signal based on the first phase difference for adjusting a phase of at least one of the first transmission signal or the second transmission signal.
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公开(公告)号:US20230146632A1
公开(公告)日:2023-05-11
申请号:US17982644
申请日:2022-11-08
Inventor: Sewon Kim , Kisuk Kang , Kyeongsu Lee , Myeonghwan Lee , Sangwook Han
IPC: H01M4/40 , H01M4/04 , H01M4/36 , H01M10/0562 , H01M4/38
CPC classification number: H01M4/405 , H01M4/0404 , H01M4/364 , H01M10/0562 , H01M4/382 , H01M2004/021
Abstract: An anode-solid electrolyte sub-assembly for an all-solid secondary battery, the anode-solid electrolyte sub-assembly including: an anode current collector; an anode material layer on the anode current collector; and a solid electrolyte on the anode material layer and opposite the current collector, wherein the anode material layer includes an interlayer, which contacts the solid electrolyte and includes a composite including a first metal material; and a first anode active material layer on the interlayer and opposite the anode current collector, the first anode active material layer including a lithium metal, a lithium alloy, or a combination thereof, wherein the lithium metal or the lithium alloy have a particle size greater than the particle size of the first metal material.
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公开(公告)号:US11356106B2
公开(公告)日:2022-06-07
申请号:US17334077
申请日:2021-05-28
Applicant: Samsung Electronics Co., Ltd.
Inventor: Shinwoong Kim , Myounggyun Kim , Joonhee Lee , Sangwook Han
Abstract: An electronic device includes a phase locked loop configured to perform a two-point modulation operation on a data signal by using first and second modulation paths, and the phase locked loop is configured to generate, based on a differential value of a first phase error signal generated in the first modulation path, a gain for adjusting a frequency variation of the data signal through the second modulation path so as to match with the frequency variation of the data signal through the first modulation path.
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公开(公告)号:US09948301B2
公开(公告)日:2018-04-17
申请号:US15211459
申请日:2016-07-15
Applicant: Samsung Electronics Co., Ltd.
Inventor: Sangwook Han , Thomas Byunghak Cho , Jaehyun Lim , Sung-Jun Lee , Joonhee Lee , Jongwon Choi
IPC: H03L5/00 , H03K19/0175 , H01L27/02
CPC classification number: H03K19/017509 , H01L27/0248
Abstract: An integrated circuit (IC), a method of testing the IC, and a method of manufacturing the IC are provided. The IC includes analog circuitry, digital circuitry, at least one first connector, and a switching unit operatively coupled with the at least one first connector and configured to, if a first signal is received, couple the analog circuitry and the at least one first connector, and, if a second signal is received, couple the digital circuitry and the at least one first connector.
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公开(公告)号:US20230308123A1
公开(公告)日:2023-09-28
申请号:US18063301
申请日:2022-12-08
Applicant: Samsung Electronics Co., Ltd.
Inventor: Youngmin KIM , Hongjong Park , Sangmin Yoo , Sangwook Han
CPC classification number: H04B1/0458 , H03H7/38 , H04B1/0483 , H04B1/18
Abstract: A CMOS chip includes a signal converting circuit configured to convert a baseband signal and an RF signal, a plurality of ports through which the RF signal is transmitted or received, the plurality of ports being respectively included in a first transmission path, a second transmission path, and a reception path, and a plurality of matching networks connected to the signal converting circuit, the plurality of matching networks being respectively connected to the plurality of ports, a first matching network among the plurality of matching networks including an external matching network, and the external matching network being configured to perform an impedance matching of a compound semiconductor device.
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