公开(公告)号：US11386974B2

公开(公告)日：2022-07-12

申请号：US17147851

申请日：2021-01-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sehwan Park ,  Jinyoung Kim ,  Ilhan Park ,  Kyoman Kang ,  Sangwan Nam

IPC: G11C16/28 ,  G11C29/50 ,  G11C29/44 ,  G11C7/10 ,  G11C8/18 ,  G11C29/12

Abstract: A non-volatile memory device includes a memory cell array including a plurality of memory blocks that includes a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a row decoder configured to select one among the plurality of memory blocks, based on an address, a voltage generator configured to apply word line voltages corresponding to selected word lines and unselected word lines, among the plurality of word lines, page buffers connected to the plurality of bit lines and configured to read data from a memory cell connected to one among the selected word lines of the selected one among the plurality of memory blocks, and a control logic configured to control the row decoder, the voltage generator, and the page buffers.

公开(公告)号：US10290343B2

公开(公告)日：2019-05-14

申请号：US15608219

申请日：2017-05-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： ChaeHoon Kim ,  Kyoman Kang ,  Tae-Hong Kwon ,  Taeyun Lee ,  Jin-Young Chun

IPC: G11C11/4091 ,  G11C5/14 ,  G11C7/06 ,  G11C16/24 ,  G11C16/26 ,  G11C16/32 ,  G11C7/12 ,  G11C13/00 ,  G11C16/04 ,  G11C27/02

Abstract: Methods of operating a memory device include at least partially charging a sensing node within a page buffer of the memory device to a first precharge voltage, by sampling a trip voltage of a sensing latch within the page buffer. Thereafter, a voltage of the sensing node is boosted from the first precharge voltage to a higher second precharge voltage. Then, a voltage of the sensing node that reflects a value of data stored in a memory cell of the memory device is developed at the sensing node. The developed voltage is then transferred to the sensing latch so that data stored by the sensing latch reflects the value of data stored in the memory cell.

公开(公告)号：US20180096718A1

公开(公告)日：2018-04-05

申请号：US15608219

申请日：2017-05-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： ChaeHoon KIM ,  Kyoman Kang ,  Tae-Hong Kwon ,  Taeyun Lee ,  Jin-Young Chun

IPC: G11C11/4091 ,  G11C7/12

CPC classification number: G11C11/4091 ,  G11C5/145 ,  G11C7/06 ,  G11C7/12 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/26 ,  G11C16/32 ,  G11C27/02 ,  G11C2013/0042 ,  G11C2013/0054

Abstract: Methods of operating a memory device include at least partially charging a sensing node within a page buffer of the memory device to a first precharge voltage, by sampling a trip voltage of a sensing latch within the page buffer. Thereafter, a voltage of the sensing node is boosted from the first precharge voltage to a higher second precharge voltage. Then, a voltage of the sensing node that reflects a value of data stored in a memory cell of the memory device is developed at the sensing node. The developed voltage is then transferred to the sensing latch so that data stored by the sensing latch reflects the value of data stored in the memory cell.

公开(公告)号：US12002518B2

公开(公告)日：2024-06-04

申请号：US17710283

申请日：2022-03-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yongsung Cho ,  Kyoman Kang ,  Minhwi Kim ,  Ilhan Park ,  Jinyoung Chun

IPC: G11C16/00 ,  G11C16/04 ,  G11C16/24 ,  G11C16/26

CPC classification number: G11C16/24 ,  G11C16/0483 ,  G11C16/26

Abstract: A memory device is provided. The memory device includes: a memory cell array including a plurality of memory cells; a page buffer circuit connected to the memory cell array through a plurality of bit lines and including a page buffer connected to each of the plurality of bit lines, the page buffer including at least one first latch for storing data based on a voltage level of a first sensing node; and a control circuit configured to adjust a level of a voltage signal provided to the page buffer circuit. The page buffer includes a trip control transistor arranged between the at least one first latch and the first sensing node, and wherein the control circuit is further configured to, based on a read operation being performed on the memory cell array, control a trip control voltage to be provided to a gate of the trip control transistor. A level of the trip control voltage varies according to a temperature of the memory device.

公开(公告)号：US11804280B2

公开(公告)日：2023-10-31

申请号：US17749607

申请日：2022-05-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sehwan Park ,  Jinyoung Kim ,  Ilhan Park ,  Kyoman Kang ,  Sangwan Nam

IPC: G11C29/50 ,  G11C16/28 ,  G11C7/10 ,  G11C8/18 ,  G11C29/44 ,  G11C29/12

CPC classification number: G11C29/50004 ,  G11C7/1039 ,  G11C7/1045 ,  G11C7/1057 ,  G11C7/1084 ,  G11C8/18 ,  G11C16/28 ,  G11C29/44 ,  G11C2029/1202 ,  G11C2029/1204

Abstract: A non-volatile memory device includes a memory cell array including a plurality of memory blocks that includes a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a row decoder configured to select one among the plurality of memory blocks, based on an address, a voltage generator configured to apply word line voltages corresponding to selected word lines and unselected word lines, among the plurality of word lines, page buffers connected to the plurality of bit lines and configured to read data from a memory cell connected to one among the selected word lines of the selected one among the plurality of memory blocks, and a control logic configured to control the row decoder, the voltage generator, and the page buffers.

公开(公告)号：US20230055963A1

公开(公告)日：2023-02-23

申请号：US17710283

申请日：2022-03-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yongsung CHO ,  Kyoman Kang ,  Minhwi Kim ,  Ilhan Park ,  Jinyoung Chun

IPC: G11C16/24 ,  G11C16/04 ,  G11C16/26

Abstract: A memory device is provided. The memory device includes: a memory cell array including a plurality of memory cells; a page buffer circuit connected to the memory cell array through a plurality of bit lines and including a page buffer connected to each of the plurality of bit lines, the page buffer including at least one first latch for storing data based on a voltage level of a first sensing node; and a control circuit configured to adjust a level of a voltage signal provided to the page buffer circuit. The page buffer includes a trip control transistor arranged between the at least one first latch and the first sensing node, and wherein the control circuit is further configured to, based on a read operation being performed on the memory cell array, control a trip control voltage to be provided to a gate of the trip control transistor. A level of the trip control voltage varies according to a temperature of the memory device.

公开(公告)号：US20220028478A1

公开(公告)日：2022-01-27

申请号：US17147851

申请日：2021-01-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sehwan PARK ,  Jinyoung Kim ,  Ilhan Park ,  Kyoman Kang ,  Sangwan Nam

IPC: G11C29/50 ,  G11C29/44 ,  G11C7/10 ,  G11C8/18

Abstract: A non-volatile memory device includes a memory cell array including a plurality of memory blocks that includes a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a row decoder configured to select one among the plurality of memory blocks, based on an address, a voltage generator configured to apply word line voltages corresponding to selected word lines and unselected word lines, among the plurality of word lines, page buffers connected to the plurality of bit lines and configured to read data from a memory cell connected to one among the selected word lines of the selected one among the plurality of memory blocks, and a control logic configured to control the row decoder, the voltage generator, and the page buffers.

公开(公告)号：US12300329B2

公开(公告)日：2025-05-13

申请号：US17881039

申请日：2022-08-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongsung Cho ,  Minjae Seo ,  Kyoman Kang ,  Byungsoo Kim

IPC: G11C16/30 ,  G11C16/04 ,  G11C16/08 ,  G11C16/26

Abstract: Provided is a memory device with a vertical channel structure. The memory device includes a memory cell array including a plurality of memory cells and a plurality of string selection lines, a negative charge pump configured to generate a bias voltage of a negative level, to be applied to at least one of the plurality of string selection lines, and a control logic circuit configured to apply, for a first period, a prepulse voltage to at least one unselected string selection line among the plurality of string selection lines excluding a selected string selection line to which a memory cell selected from among the plurality of memory cells is connected and thereafter apply the bias voltage to the at least one unselected string selection line so as to perform a read operation on the selected memory cell.

公开(公告)号：US12094552B2

公开(公告)日：2024-09-17

申请号：US18374026

申请日：2023-09-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sehwan Park ,  Jinyoung Kim ,  Ilhan Park ,  Kyoman Kang ,  Sangwan Nam

IPC: G11C29/50 ,  G11C7/10 ,  G11C8/18 ,  G11C16/28 ,  G11C29/44 ,  G11C29/12

CPC classification number: G11C29/50004 ,  G11C7/1039 ,  G11C7/1045 ,  G11C7/1057 ,  G11C7/1084 ,  G11C8/18 ,  G11C16/28 ,  G11C29/44 ,  G11C2029/1202 ,  G11C2029/1204

Abstract: A non-volatile memory device includes a memory cell array including a plurality of memory blocks that includes a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a row decoder configured to select one among the plurality of memory blocks, based on an address, a voltage generator configured to apply word line voltages corresponding to selected word lines and unselected word lines, among the plurality of word lines, page buffers connected to the plurality of bit lines and configured to read data from a memory cell connected to one among the selected word lines of the selected one among the plurality of memory blocks, and a control logic configured to control the row decoder, the voltage generator, and the page buffers.

公开(公告)号：US11600350B2

公开(公告)日：2023-03-07

申请号：US17509678

申请日：2021-10-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungbum Kim ,  Kyoman Kang

IPC: G11C29/14 ,  G11C29/12 ,  G11C29/46 ,  G11C7/06 ,  G11C7/10

Abstract: In a method of testing a nonvolatile memory device including a first semiconductor layer in which and a second semiconductor layer is formed prior to the first semiconductor layer, circuit elements including a page buffer circuit are provided in the second semiconductor layer, an on state of nonvolatile memory cells which are not connected to the page buffer circuit is mimicked by providing a conducting path between an internal node of a bit-line connection circuit connected between a sensing node and a bit-line node of the page buffer circuit and a voltage terminal to receive a first voltage, a sensing and latching operation with the on state being mimicked is performed in the page buffer circuit and a determination is made as to whether the page buffer circuit operates normally is made based on a result of the sensing and latching operation.