公开(公告)号：US20210272957A1

公开(公告)日：2021-09-02

申请号：US17321760

申请日：2021-05-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehyun Lee ,  Jonghan Lee ,  Seonghwa Park ,  Jongha Park ,  Jaehoon Woo ,  Dabok Jeong

IPC: H01L27/092 ,  H01L29/06 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78

Abstract: An integrated circuit semiconductor device includes a first region including a first transistor and a second region in contact with the first region in a second direction. The first transistor includes a first active fin extending in a first direction, a first gate dielectric layer extending from the first active fin onto a first isolation layer in the second direction, and a first gate electrode on the first gate dielectric layer. The second region includes a second transistor including a second active fin extending in the first direction, a second gate dielectric layer extending from the second active fin onto a second isolation layer in the second direction, and a second gate electrode on the second gate dielectric layer. The integrated circuit semiconductor device includes a gate dielectric layer removal region proximate a boundary between the first region and the second region.

公开(公告)号：US11043495B2

公开(公告)日：2021-06-22

申请号：US16718799

申请日：2019-12-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehyun Lee ,  Jonghan Lee ,  Seonghwa Park ,  Jongha Park ,  Jaehoon Woo ,  Dabok Jeong

IPC: H01L27/092 ,  H01L29/06 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78

Abstract: An integrated circuit semiconductor device includes a first region including a first transistor and a second region in contact with the first region in a second direction. The first transistor includes a first active fin extending in a first direction, a first gate dielectric layer extending from the first active fin onto a first isolation layer in the second direction, and a first gate electrode on the first gate dielectric layer. The second region includes a second transistor including a second active fin extending in the first direction, a second gate dielectric layer extending from the second active fin onto a second isolation layer in the second direction, and a second gate electrode on the second gate dielectric layer. The integrated circuit semiconductor device includes a gate dielectric layer removal region proximate a boundary between the first region and the second region.

公开(公告)号：US20200083220A1

公开(公告)日：2020-03-12

申请号：US16382439

申请日：2019-04-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seonghwa Park ,  Hongbae Park ,  Jaehyun Lee ,  Jonghan Lee ,  Dabok Jeong ,  Minseok Jo

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/308 ,  H01L21/8234

Abstract: A semiconductor device includes a first gate pattern and a second gate pattern on a substrate, the first gate pattern and the second gate pattern being spaced apart from each other, and a separation pattern that separates the first gate pattern and the second gate pattern from each other. The first gate pattern includes a first high-k dielectric pattern and a first metal-containing pattern on the first high-k dielectric pattern, the first metal-containing pattern covering a sidewall of the first high-k dielectric pattern. The second gate pattern includes a second high-k dielectric pattern and a second metal-containing pattern on the second high-k dielectric pattern, and the separation pattern is in direct contact with the first metal-containing pattern and spaced apart from the first high-k dielectric pattern.

公开(公告)号：US20200035678A1

公开(公告)日：2020-01-30

申请号：US16592330

申请日：2019-10-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongsoo LEE ,  Wonkeun Chung ,  Hoonjoo Na ,  Suyoung Bae ,  Jaeyeol Song ,  Jonghan Lee ,  HyungSuk Jung ,  Sangjin Hyun

IPC: H01L27/092 ,  H01L29/786 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L21/8238

Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device comprises a first transistor on a substrate, and a second transistor on the substrate. Each of the first and second transistors includes a plurality of semiconductor patterns vertically stacked on the substrate and vertically spaced apart from each other, and a gate dielectric pattern and a work function pattern filling a space between the semiconductor patterns. The work function pattern of the first transistor includes a first work function metal layer, the work function pattern of the second transistor includes the first work function metal layer and a second work function metal layer, the first work function metal layer of each of the first and second transistors has a work function greater than that of the second work function metal layer, and the first transistor has a threshold voltage less than that of the second transistor.

公开(公告)号：US12021080B2

公开(公告)日：2024-06-25

申请号：US18353214

申请日：2023-07-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongsoo Lee ,  Wonkeun Chung ,  Hoonjoo Na ,  Suyoung Bae ,  Jaeyeol Song ,  Jonghan Lee ,  HyungSuk Jung ,  Sangjin Hyun

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/786

CPC classification number: H01L27/0922 ,  H01L21/823842 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/78696

Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device comprises a first transistor on a substrate, and a second transistor on the substrate. Each of the first and second transistors includes a plurality of semiconductor patterns vertically stacked on the substrate and vertically spaced apart from each other, and a gate dielectric pattern and a work function pattern filling a space between the semiconductor patterns. The work function pattern of the first transistor includes a first work function metal layer, the work function pattern of the second transistor includes the first work function metal layer and a second work function metal layer, the first work function metal layer of each of the first and second transistors has a work function greater than that of the second work function metal layer, and the first transistor has a threshold voltage less than that of the second transistor.

公开(公告)号：US11289478B2

公开(公告)日：2022-03-29

申请号：US16382439

申请日：2019-04-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seonghwa Park ,  Hongbae Park ,  Jaehyun Lee ,  Jonghan Lee ,  Dabok Jeong ,  Minseok Jo

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/308

Abstract: A semiconductor device includes a first gate pattern and a second gate pattern on a substrate, the first gate pattern and the second gate pattern being spaced apart from each other, and a separation pattern that separates the first gate pattern and the second gate pattern from each other. The first gate pattern includes a first high-k dielectric pattern and a first metal-containing pattern on the first high-k dielectric pattern, the first metal-containing pattern covering a sidewall of the first high-k dielectric pattern. The second gate pattern includes a second high-k dielectric pattern and a second metal-containing pattern on the second high-k dielectric pattern, and the separation pattern is in direct contact with the first metal-containing pattern and spaced apart from the first high-k dielectric pattern.

公开(公告)号：US11664379B2

公开(公告)日：2023-05-30

申请号：US17321760

申请日：2021-05-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehyun Lee ,  Jonghan Lee ,  Seonghwa Park ,  Jongha Park ,  Jaehoon Woo ,  Dabok Jeong

IPC: H01L27/092 ,  H01L29/06 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/66795 ,  H01L29/785

Abstract: An integrated circuit semiconductor device includes a first region including a first transistor and a second region in contact with the first region in a second direction. The first transistor includes a first active fin extending in a first direction, a first gate dielectric layer extending from the first active fin onto a first isolation layer in the second direction, and a first gate electrode on the first gate dielectric layer. The second region includes a second transistor including a second active fin extending in the first direction, a second gate dielectric layer extending from the second active fin onto a second isolation layer in the second direction, and a second gate electrode on the second gate dielectric layer. The integrated circuit semiconductor device includes a gate dielectric layer removal region proximate a boundary between the first region and the second region.

公开(公告)号：US11121131B2

公开(公告)日：2021-09-14

申请号：US16592330

申请日：2019-10-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongsoo Lee ,  Wonkeun Chung ,  Hoonjoo Na ,  Suyoung Bae ,  Jaeyeol Song ,  Jonghan Lee ,  HyungSuk Jung ,  Sangjin Hyun

IPC: H01L27/092 ,  H01L29/786 ,  H01L29/49 ,  H01L29/51 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L21/8238

Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device comprises a first transistor on a substrate, and a second transistor on the substrate. Each of the first and second transistors includes a plurality of semiconductor patterns vertically stacked on the substrate and vertically spaced apart from each other, and a gate dielectric pattern and a work function pattern filling a space between the semiconductor patterns. The work function pattern of the first transistor includes a first work function metal layer, the work function pattern of the second transistor includes the first work function metal layer and a second work function metal layer, the first work function metal layer of each of the first and second transistors has a work function greater than that of the second work function metal layer, and the first transistor has a threshold voltage less than that of the second transistor.

公开(公告)号：US10811505B2

公开(公告)日：2020-10-20

申请号：US15990983

申请日：2018-05-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jonghan Lee ,  Wandon Kim ,  Jaeyeol Song ,  Jeonghyuk Yim ,  HyungSuk Jung

IPC: H01L29/423 ,  H01L27/088 ,  H01L29/51 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/768

Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device comprises a gate electrode on a substrate, an upper capping pattern on the gate electrode, and a lower capping pattern between the gate electrode and the upper capping pattern. The lower capping pattern comprises a first portion between the gate electrode and the upper capping pattern, and a plurality of second portions extending from the first portion onto corresponding side surfaces of the upper capping pattern. The upper capping pattern covers a topmost surface of each of the second portions.

公开(公告)号：US10461167B2

公开(公告)日：2019-10-29

申请号：US15861949

申请日：2018-01-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongsoo Lee ,  Wonkeun Chung ,  Hoonjoo Na ,  Suyoung Bae ,  Jaeyeol Song ,  Jonghan Lee ,  HyungSuk Jung ,  Sangjin Hyun

IPC: H01L29/49 ,  H01L21/82 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L29/06 ,  H01L29/36

Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device comprises a first transistor on a substrate, and a second transistor on the substrate. Each of the first and second transistors includes a plurality of semiconductor patterns vertically stacked on the substrate and vertically spaced apart from each other, and a gate dielectric pattern and a work function pattern filling a space between the semiconductor patterns. The work function pattern of the first transistor includes a first work function metal layer, the work function pattern of the second transistor includes the first work function metal layer and a second work function metal layer, the first work function metal layer of each of the first and second transistors has a work function greater than that of the second work function metal layer, and the first transistor has a threshold voltage less than that of the second transistor.