公开(公告)号：US20220157382A1

公开(公告)日：2022-05-19

申请号：US17523337

申请日：2021-11-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JAEHO AHN ,  JIWON KIM ,  SUNGMIN HWANG ,  JOONSUNG LIM ,  SUKKANG SUNG

IPC: G11C16/10 ,  H01L23/48 ,  G11C16/26 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: A semiconductor memory device includes: a semiconductor substrate having a first surface and a second surface opposing each other; a back-side insulating layer below the second surface of the semiconductor substrate; an external input/output conductive pattern below the back-side insulating layer; a circuit device including a gate electrode and a source/drain region, on the first surface of the semiconductor substrate; an internal input/output conductive pattern on the first surface of the semiconductor substrate, the internal input/output conductive pattern having at least a portion disposed on the same level as at least a portion of the gate electrode; a through-electrode structure penetrating through the semiconductor substrate and the back-side insulating layer and electrically connected to the internal input/output conductive pattern and the external input/output conductive pattern; and a memory cell array region disposed on a level higher than the circuit device, on the first surface of the semiconductor substrate.

公开(公告)号：US20240237340A1

公开(公告)日：2024-07-11

申请号：US18219697

申请日：2023-07-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： JIWON KIM ,  Ahreum Lee ,  JOONYOUNG KWON ,  Dohyung Kim ,  JUNHYOUNG KIM ,  SUKKANG SUNG

IPC: H10B43/27 ,  H01L23/528 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

CPC classification number: H10B43/27 ,  H01L23/5283 ,  H01L25/0655 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

Abstract: A semiconductor device includes a cell region in which a channel structure is disposed and memory cells arranged in three dimensions are disposed, a cell contact region in which a cell contact plug is disposed, a common source line contact region in which a common source line contact plug is disposed, an input and output contact region in which an input and output contact plug is disposed, a word line cut region separating word lines of the cell region from word lines of a neighboring cell region, a common source line layer connecting the channel structure and the common source line contact plug, and an input and output pad connected to the input and output contact plug. The common source line layer and the input and output pad are disposed at the same vertical level.

公开(公告)号：US20240237362A9

公开(公告)日：2024-07-11

申请号：US18323440

申请日：2023-05-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： JIWON KIM ,  Dohyung Kim ,  Jiyoung Kim ,  Sukkang Sung

IPC: H10B80/00 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H10B80/00 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A three-dimensional semiconductor memory device may include a peripheral structure and a cell structure on the peripheral structure. The cell structure may include a substrate having first and second surfaces, which are opposite to each other, a stack including gate electrodes, which are stacked on the first surface of the substrate, an insulating layer on the second surface of the substrate, a penetration contact plug penetrating the first surface of the substrate, a first gapfill conductive pattern provided to penetrate the second surface of the substrate and the insulating layer and spaced apart from the penetration contact plug, a second gapfill conductive pattern provided to penetrate the second surface of the substrate and the insulating layer and connected to the penetration contact plug, a first gapfill spacer between the first gapfill conductive pattern and the substrate, and a second gapfill spacer between the second gapfill conductive pattern and the substrate.

公开(公告)号：US20240138157A1

公开(公告)日：2024-04-25

申请号：US18323440

申请日：2023-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： JIWON KIM ,  Dohyung Kim ,  Jiyoung Kim ,  Sukkang Sung

IPC: H10B80/00 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H10B80/00 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A three-dimensional semiconductor memory device may include a peripheral structure and a cell structure on the peripheral structure. The cell structure may include a substrate having first and second surfaces, which are opposite to each other, a stack including gate electrodes, which are stacked on the first surface of the substrate, an insulating layer on the second surface of the substrate, a penetration contact plug penetrating the first surface of the substrate, a first gapfill conductive pattern provided to penetrate the second surface of the substrate and the insulating layer and spaced apart from the penetration contact plug, a second gapfill conductive pattern provided to penetrate the second surface of the substrate and the insulating layer and connected to the penetration contact plug, a first gapfill spacer between the first gapfill conductive pattern and the substrate, and a second gapfill spacer between the second gapfill conductive pattern and the substrate.