公开(公告)号：US11309393B2

公开(公告)日：2022-04-19

申请号：US16404857

申请日：2019-05-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chang-yeon Lee ,  Jin-wook Lee ,  Min-chan Gwak ,  Kye-Hyun Baek ,  Hong-bae Park

IPC: H01L29/417 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78

Abstract: An integrated circuit device including a substrate; a fin-type active region protruding from the substrate; a gate line intersecting the fin-type active region and covering a top surface and side walls thereof; a gate insulating capping layer covering the gate line; source/drain regions at sides of the gate line on the fin-type active region; first conductive plugs connected to the source/drain regions; a hard mask layer covering the first conductive plugs; and a second conductive plug between the first conductive plugs, the second conductive plug connected to the gate line by passing through the gate insulating capping layer and having a top surface higher than the top surface of each first conductive plug, wherein the hard mask layer protrudes from the first conductive plugs and toward the second conductive plug so that a portion of the hard mask layer overhangs from an edge of the first conductive plugs.

公开(公告)号：US10014304B2

公开(公告)日：2018-07-03

申请号：US15333491

申请日：2016-10-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hong-bae Park ,  Ja-hum Ku ,  Myeong-cheol Kim ,  Jin-wook Lee ,  Sung-kee Han

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/8234 ,  H01L27/11 ,  H01L27/092 ,  H01L27/02 ,  H01L21/8238 ,  H01L21/02 ,  H01L23/528

CPC classification number: H01L27/1104 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/845 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/785

Abstract: A method includes providing a plurality of active regions on a substrate, and at least a first device isolation layer between two of the plurality of active regions, wherein the plurality of active regions extend in a first direction; providing a gate layer extending in a second direction, the gate layer forming a plurality of gate lines including a first gate line and a second gate line extending in a straight line with respect to each other and having a space therebetween, each of the first gate line and second gate line crossing at least one of the active regions, providing an insulation layer covering the first device isolation layer and covering the active region around each of the first and second gate lines; and providing an inter-gate insulation region in the space between the first gate line and the second gate line.

公开(公告)号：US10651179B2

公开(公告)日：2020-05-12

申请号：US15992623

申请日：2018-05-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hong-bae Park ,  Ja-hum Ku ,  Myeong-cheol Kim ,  Jin-wook Lee ,  Sung-kee Han

IPC: H01L27/11 ,  H01L27/092 ,  H01L27/02 ,  H01L21/8238 ,  H01L27/12 ,  H01L21/84 ,  H01L29/78 ,  H01L21/02 ,  H01L23/528 ,  H01L29/06 ,  H01L29/66

Abstract: A method includes providing a plurality of active regions on a substrate, and at least a first device isolation layer between two of the plurality of active regions, wherein the plurality of active regions extend in a first direction; providing a gate layer extending in a second direction, the gate layer forming a plurality of gate lines including a first gate line and a second gate line extending in a straight line with respect to each other and having a space therebetween, each of the first gate line and second gate line crossing at least one of the active regions, providing an insulation layer covering the first device isolation layer and covering the active region around each of the first and second gate lines; and providing an inter-gate insulation region in the space between the first gate line and the second gate line.

公开(公告)号：US09240483B2

公开(公告)日：2016-01-19

申请号：US13684655

申请日：2012-11-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： June-hee Lee ,  Jae-yeol Song ,  Hye-Ian Lee ,  Hong-bae Park ,  Sang-jin Hyun

IPC: H01L21/70 ,  H01L29/78 ,  H01L27/088

CPC classification number: H01L29/785 ,  H01L27/0886

Abstract: A semiconductor device includes a fin-type active region; a gate dielectric layer covering an upper surface and opposite lateral surfaces of the fin-type active region; and a gate line extending on the gate dielectric layer to cover the upper surface and opposite lateral surfaces of the fin-type active region and to cross the fin-type active region. The gate line includes an aluminum (Al) doped metal-containing layer extending to cover the upper surface and opposite lateral surfaces of the fin-type active region to a uniform thickness, and a gap-fill metal layer extending on the Al doped metal-containing layer over the fin-type active region. Related fabrication methods are also described.

Abstract translation: 半导体器件包括鳍型有源区; 覆盖所述鳍状有源区的上表面和相对的侧表面的栅介电层; 以及在所述栅极电介质层上延伸以覆盖所述鳍状有源区的上表面和相对的侧表面并跨越所述鳍型有源区的栅极线。 栅极线包括铝（Al）掺杂的含金属层，其延伸以覆盖翅片型有源区的上表面和相对的侧表面至均匀的厚度;以及间隙填充金属层，其在Al掺杂的金属 - 在翅片型有源区域上方。 还描述了相关的制造方法。

公开(公告)号：US20130277748A1

公开(公告)日：2013-10-24

申请号：US13684655

申请日：2012-11-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： June-Hee LEE ,  Jae-yeol Song ,  Hye-Ian Lee ,  Hong-bae Park ,  Sang-jin Hyun

IPC: H01L29/78

CPC classification number: H01L29/785 ,  H01L27/0886

Abstract: A semiconductor device includes a fin-type active region; a gate dielectric layer covering an upper surface and opposite lateral surfaces of the fin-type active region; and a gate line extending on the gate dielectric layer to cover the upper surface and opposite lateral surfaces of the fin-type active region and to cross the fin-type active region. The gate line includes an aluminum (Al) doped metal-containing layer extending to cover the upper surface and opposite lateral surfaces of the fin-type active region to a uniform thickness, and a gap-fill metal layer extending on the Al doped metal-containing layer over the fin-type active region. Related fabrication methods are also described.

Abstract translation: 半导体器件包括鳍型有源区; 覆盖所述鳍状有源区的上表面和相对的侧表面的栅介电层; 以及在所述栅极电介质层上延伸以覆盖所述鳍状有源区的上表面和相对的侧表面并跨越所述鳍型有源区的栅极线。 栅极线包括铝（Al）掺杂的含金属层，其延伸以覆盖翅片型有源区的上表面和相对的侧表面至均匀的厚度;以及间隙填充金属层，其在Al掺杂的金属 - 在翅片型有源区域上方。 还描述了相关的制造方法。

公开(公告)号：US12015063B2

公开(公告)日：2024-06-18

申请号：US17707036

申请日：2022-03-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chang-yeon Lee ,  Jin-wook Lee ,  Min-chan Gwak ,  Kye-Hyun Baek ,  Hong-bae Park

IPC: H01L29/417 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/0886 ,  H01L29/7851

Abstract: An integrated circuit device including a substrate; a fin-type active region protruding from the substrate; a gate line intersecting the fin-type active region and covering a top surface and side walls thereof; a gate insulating capping layer covering the gate line; source/drain regions at sides of the gate line on the fin-type active region; first conductive plugs connected to the source/drain regions; a hard mask layer covering the first conductive plugs; and a second conductive plug between the first conductive plugs, the second conductive plug connected to the gate line by passing through the gate insulating capping layer and having a top surface higher than the top surface of each first conductive plug, wherein the hard mask layer protrudes from the first conductive plugs and toward the second conductive plug so that a portion of the hard mask layer overhangs from an edge of the first conductive plugs.

公开(公告)号：US09236313B2

公开(公告)日：2016-01-12

申请号：US14563420

申请日：2014-12-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hoon-joo Na ,  Yu-gyun Shin ,  Hong-bae Park ,  Hag-ju Cho ,  Sug-hun Hong ,  Sang-jin Hyun ,  Hyung-seok Hong

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/28 ,  H01L29/51 ,  H01L21/3213 ,  H01L21/324 ,  H01L21/8234

CPC classification number: H01L21/823828 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/32133 ,  H01L21/324 ,  H01L21/823437 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0922 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518

Abstract: A method of fabricating a semiconductor device having a dual gate allows for the gates to have a wide variety of threshold voltages. The method includes forming a gate insulation layer, a first capping layer, and a barrier layer in the foregoing sequence across a first region and a second region on a substrate, exposing the gate insulation layer on the first region by removing the first capping layer and the barrier layer from the first region, forming a second capping layer on the gate insulation layer in the first region and on the barrier layer in the second region, and thermally processing the substrate on which the second capping layer is formed. The thermal processing causes material of the second capping layer to spread into the gate insulation layer in the first region and material of the first capping layer to spread into the gate insulation layer in the second region. Thus, devices having different threshold voltages can be formed in the first and second regions.

公开(公告)号：US20150093888A1

公开(公告)日：2015-04-02

申请号：US14563420

申请日：2014-12-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hoon-joo Na ,  Yu-gyun Shin ,  Hong-bae Park ,  Hag-ju Cho ,  Sug-hun Hong ,  Sang-jin Hyun ,  Hyung-seok Hong

IPC: H01L21/8238 ,  H01L21/8234 ,  H01L21/3213 ,  H01L21/324 ,  H01L29/51

CPC classification number: H01L21/823828 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/32133 ,  H01L21/324 ,  H01L21/823437 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0922 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518

Abstract: A method of fabricating a semiconductor device having a dual gate allows for the gates to have a wide variety of threshold voltages. The method includes forming a gate insulation layer, a first capping layer, and a barrier layer in the foregoing sequence across a first region and a second region on a substrate, exposing the gate insulation layer on the first region by removing the first capping layer and the barrier layer from the first region, forming a second capping layer on the gate insulation layer in the first region and on the barrier layer in the second region, and thermally processing the substrate on which the second capping layer is formed. The thermal processing causes material of the second capping layer to spread into the gate insulation layer in the first region and material of the first capping layer to spread into the gate insulation layer in the second region. Thus, devices having different threshold voltages can be formed in the first and second regions.

Abstract translation: 制造具有双栅极的半导体器件的方法允许栅极具有各种阈值电压。 该方法包括：跨越衬底上的第一区域和第二区域以上述顺序形成栅极绝缘层，第一覆盖层和阻挡层，通过去除第一覆盖层和暴露第一区域上的栅极绝缘层; 所述阻挡层从所述第一区域形成在所述第一区域中的所述栅极绝缘层上和所述第二区域中的所述势垒层上形成第二覆盖层，并对形成有所述第二覆盖层的所述基板进行热处理。 热处理使得第二覆盖层的材料扩散到第一区域中的栅极绝缘层中，并且第一覆盖层的材料扩散到第二区域中的栅极绝缘层中。 因此，可以在第一和第二区域中形成具有不同阈值电压的器件。