公开(公告)号：US20220059420A1

公开(公告)日：2022-02-24

申请号：US17160462

申请日：2021-01-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hansung RYU

IPC: H01L23/053 ,  H01L25/065 ,  H01L23/367 ,  H01L23/00

Abstract: A semiconductor package includes a substrate, a semiconductor stack mounted on the substrate, and a stiffener surrounding the semiconductor stack, the stiffener having an octagonal shape at an edge of an upper surface thereof. A minimum distance from one angular point of an upper surface of the substrate to the stiffener is determined based on the thickness of the substrate.

公开(公告)号：US20240063077A1

公开(公告)日：2024-02-22

申请号：US18137809

申请日：2023-04-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongbeom PARK ,  Hansung RYU ,  Kangjoon LEE

IPC: H01L23/367 ,  H01L25/18 ,  H10B80/00 ,  H01L23/00 ,  H01L23/427 ,  H01L23/433

CPC classification number: H01L23/367 ,  H01L25/18 ,  H10B80/00 ,  H01L24/06 ,  H01L24/05 ,  H01L24/16 ,  H01L24/17 ,  H01L23/427 ,  H01L23/433 ,  H01L25/0657

Abstract: A semiconductor package includes a package base substrate, a first semiconductor chip on the package base substrate, a second semiconductor chip on the package base substrate, and spaced apart from the first semiconductor chip in a first horizontal direction, a reinforcing structure on the package base substrate, and spaced apart from the second semiconductor chip in a second horizontal direction intersecting the first horizontal direction, and a heat transfer pad between the second semiconductor chip and the reinforcing structure.

公开(公告)号：US20200273723A1

公开(公告)日：2020-08-27

申请号：US15930935

申请日：2020-05-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chanho LEE ,  Hyunsoo CHUNG ,  Hansung RYU ,  InYoung LEE

IPC: H01L21/50 ,  H01L23/48 ,  H01L23/00 ,  H01L23/58 ,  H01L23/373 ,  H01L21/48 ,  H01L21/02 ,  H01L23/544 ,  H01L25/065 ,  H01L21/768

Abstract: A semiconductor device including a substrate, an insulating layer on the substrate and including a trench, at least one via structure penetrating the substrate and protruding above a bottom surface of the trench, and a conductive structure surrounding the at least one via structure in the trench may be provided.

公开(公告)号：US20180315620A1

公开(公告)日：2018-11-01

申请号：US15815032

申请日：2017-11-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chanho LEE ,  Hyunsoo CHUNG ,  Hansung RYU ,  InYoung LEE

IPC: H01L21/50 ,  H01L23/48 ,  H01L23/00 ,  H01L21/02 ,  H01L23/373 ,  H01L21/48 ,  H01L23/58

CPC classification number: H01L21/50 ,  H01L21/02118 ,  H01L21/486 ,  H01L23/3128 ,  H01L23/373 ,  H01L23/481 ,  H01L23/544 ,  H01L23/58 ,  H01L24/02 ,  H01L25/0657 ,  H01L2223/54426

Abstract: A semiconductor device including a substrate, an insulating, layer on the substrate and including a trench, at least one via structure penetrating the substrate and protruding above a bottom surface of the trench, and a conductive structure surrounding the at least one via structure in the trench may be provided.

公开(公告)号：US20230375452A1

公开(公告)日：2023-11-23

申请号：US18180533

申请日：2023-03-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hansung RYU ,  Haksung KIM ,  Gyunghwan OH ,  Heonsu KIM ,  Dongwoon PARK ,  Jeonghyeon BAEK

IPC: G01N11/00

CPC classification number: G01N11/00 ,  G01N2011/0013 ,  G01N2011/0093 ,  G01N2011/008 ,  G01N2011/0066

Abstract: An apparatus for measuring properties of a thermosetting polymer includes a body having a first chamber and a second chamber each filled with the thermosetting polymer material. A first FBG sensor is disposed in the polymer material within the first chamber and a second FBG sensor is disposed in the polymer material within the second chamber. A first dielectric constant sensor is in the first chamber, and a second dielectric constant sensor is in the second chamber. A computing device is configured to measure properties of the thermosetting polymer based on wavelength data measured using the first FBG sensor and the second FBG sensor, and a loss coefficient of the polymer material measured using the first dielectric constant sensor and the second dielectric constant sensor, while the thermosetting polymer solidifies in the first chamber and the second chamber.

公开(公告)号：US20190139785A1

公开(公告)日：2019-05-09

申请号：US16234815

申请日：2018-12-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chanho LEE ,  Hyunsoo CHUNG ,  Hansung RYU ,  Inyoung LEE

IPC: H01L21/50 ,  H01L23/00 ,  H01L23/544 ,  H01L21/02 ,  H01L25/065 ,  H01L23/48 ,  H01L23/373 ,  H01L23/58 ,  H01L21/48 ,  H01L23/31

Abstract: A semiconductor device including a substrate, an insulating layer on the substrate and including a trench, at least one via structure penetrating the substrate and protruding above a bottom surface of the trench, and a conductive structure surrounding the at least one via structure in the trench may be provided.

公开(公告)号：US20250151293A1

公开(公告)日：2025-05-08

申请号：US18738574

申请日：2024-06-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeehyun JUNG ,  Hansung RYU ,  Jongbeom PARK

IPC: H10B80/00 ,  H01L23/00 ,  H01L25/065

Abstract: A high bandwidth memory includes a base die and a memory stack on the base die. The memory stack includes a plurality of memory dies. The memory stack includes a first memory die closest to the base die among the plurality of memory dies and having a first width in a horizontal direction, and a second memory die on the first memory die and having a second width in the horizontal direction, the first width is smaller than the second width.

公开(公告)号：US20250132227A1

公开(公告)日：2025-04-24

申请号：US18621451

申请日：2024-03-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hansung RYU ,  Jongbeom PARK

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/522

Abstract: A semiconductor package may include a first semiconductor chip and a second semiconductor chip below the first semiconductor chip. The first semiconductor chip may include a first semiconductor substrate, a first semiconductor device and a first interconnection layer on a bottom surface of the first semiconductor substrate, a first via penetrating the first semiconductor substrate and electrically connected to the first interconnection layer, and a first pad on a bottom surface of the first interconnection layer. The second semiconductor chip may include a second semiconductor substrate, a second via penetrating the second semiconductor substrate, and a second pad on a top surface of the second semiconductor substrate and electrically connected to the second via. The first and second vias may be shifted from each other in a horizontal direction, and the first via may be horizontally spaced apart from the first pad, when viewed in a plan view.

公开(公告)号：US20210183663A1

公开(公告)日：2021-06-17

申请号：US17188404

申请日：2021-03-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chanho LEE ,  Hyunsoo CHUNG ,  Hansung RYU ,  InYoung LEE

IPC: H01L21/50 ,  H01L23/48 ,  H01L23/00 ,  H01L23/58 ,  H01L23/373 ,  H01L21/48 ,  H01L21/02 ,  H01L23/544 ,  H01L25/065 ,  H01L21/768

Abstract: A semiconductor device including a substrate, an insulating layer on the substrate and including a trench, at least one via structure penetrating the substrate and protruding above a bottom surface of the trench, and a conductive structure surrounding the at least one via structure in the trench may be provided.

公开(公告)号：US20160379937A1

公开(公告)日：2016-12-29

申请号：US15138441

申请日：2016-04-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： KyongSoon CHO ,  Myoungkyun KIL ,  Hansung RYU

IPC: H01L23/00 ,  H05K1/11 ,  H05K1/02 ,  H01L23/498

CPC classification number: H01L23/562 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/5386 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/0271 ,  H05K1/0298 ,  H05K1/111 ,  H05K2201/09781 ,  H05K2201/2009 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A substrate strip is provided. The substrate strip includes a core layer including first and second substrate regions spaced apart from each other and a dummy region between the first and second substrate regions, a first interconnection layer disposed on top surfaces of the first and second substrate regions, a second interconnection layer disposed on bottom surfaces of the first and second substrate regions, and a warpage control member provided on any one of a top surface and a bottom surface of the dummy region. The warpage control member includes a metal.

Abstract translation: 提供衬底条。 衬底条包括芯层，该芯层包括彼此间隔开的第一和第二衬底区域以及在第一和第二衬底区域之间的虚设区域，设置在第一和第二衬底区域的顶表面上的第一互连层，第二互连层 设置在第一和第二基板区域的底表面上，以及翘曲控制构件，设置在虚拟区域的顶表面和底表面中的任一个上。 翘曲控制构件包括金属。