公开(公告)号：US11791295B2

公开(公告)日：2023-10-17

申请号：US16795733

申请日：2020-02-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gwangjae Jeon ,  Dongkyu Kim ,  Jung-Ho Park ,  Yeonho Jang

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L23/528 ,  H01L23/532 ,  H01L23/498

CPC classification number: H01L24/11 ,  H01L21/76885 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/023 ,  H01L2224/0401 ,  H01L2224/04105

Abstract: Disclosed is a semiconductor package comprising a redistribution substrate, and a semiconductor chip on a top surface of the redistribution substrate. The redistribution substrate includes an under-bump pattern, a lower dielectric layer that covers a sidewall of the under-bump pattern, and a first redistribution pattern on the lower dielectric layer. The first redistribution pattern includes a first line part. A width at a top surface of the under-bump pattern is greater than a width at a bottom surface of the under-bump pattern. A thickness of the under-bump pattern is greater than a thickness of the first line part.

公开(公告)号：US20240421140A1

公开(公告)日：2024-12-19

申请号：US18628182

申请日：2024-04-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanghoon Lee ,  Yeongbeom Ko ,  Seokgeun Ahn ,  Juhyeon Oh ,  Gwangjae Jeon

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48

Abstract: A semiconductor package includes a buffer die, a first core die stack stacked on the buffer die, the first core die stack including at least one first intermediate core and a first gap filling portion covering an outer surface of the at least one first intermediate core, and a second core die stack stacked on the first core die stack, the second core die stack including at least one second intermediate core and a second gap filling portion covering an outer surface of the at least one second intermediate core. The first gap filling portion and the second gap filling portion are directly bonded to each other.

公开(公告)号：US11929316B2

公开(公告)日：2024-03-12

申请号：US18111100

申请日：2023-02-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongyoun Kim ,  Eungkyu Kim ,  Gwangjae Jeon

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L25/18

CPC classification number: H01L23/49838 ,  H01L21/481 ,  H01L21/4857 ,  H01L23/49822 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L21/561 ,  H01L21/563 ,  H01L23/3107 ,  H01L24/73 ,  H01L25/18 ,  H01L2224/13016 ,  H01L2224/13541 ,  H01L2224/1355 ,  H01L2224/16013 ,  H01L2224/1607 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/17055 ,  H01L2224/17517 ,  H01L2224/73204 ,  H01L2224/81345 ,  H01L2224/81815

Abstract: Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package comprises a redistribution substrate including dielectric and redistribution patterns, a first substrate pad on the redistribution substrate and penetrating the dielectric pattern to be coupled to the redistribution pattern, a second substrate pad the redistribution substrate and spaced apart from the first substrate pad, a semiconductor chip on the redistribution substrate, a first connection terminal connecting the first substrate pad to one of chip pads of the semiconductor chip, and a second connection terminal connecting the second substrate pad to another one of the chip pads of the semiconductor chip. A top surface of the second substrate pad is located at a higher level than that of a top surface of the first substrate pad. A width of the second substrate pad is less than that of the first substrate pad.

公开(公告)号：US11705341B2

公开(公告)日：2023-07-18

申请号：US17741751

申请日：2022-05-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokhyun Lee ,  Gwangjae Jeon

IPC: H01L21/48 ,  H01L23/498

CPC classification number: H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49894

Abstract: Disclosed are redistribution substrates and semiconductor packages including the same. For example, a redistribution substrate including a dielectric pattern, and a first redistribution pattern in the dielectric pattern is provided. The first redistribution pattern may include: a first via part having a first via seed pattern and a first via conductive pattern on the first via seed pattern, and a first wiring part having a first wiring seed pattern and a first wiring conductive pattern, the first wiring part being disposed on the first via part and having a horizontal width that is different from a horizontal width of the first via part. Additionally, the first wiring seed pattern may cover a bottom surface and a sidewall surface of the first wiring conductive pattern, and the first via conductive pattern is directly connected to the first wiring conductive pattern.

公开(公告)号：US11056461B2

公开(公告)日：2021-07-06

申请号：US16748138

申请日：2020-01-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeonho Jang ,  Gwangjae Jeon ,  Dongkyu Kim ,  Jungho Park ,  Seokhyun Lee

IPC: H01L21/56 ,  H01L23/00 ,  H01L21/78

Abstract: Provided is a method of manufacturing a semiconductor package including providing a carrier substrate, providing sacrificial layer on the carrier substrate, the sacrificial layer including a first sacrificial layer and a second sacrificial layer, providing a redistribution wiring layer on the sacrificial layer, providing a plurality of semiconductor chips on the redistribution wiring layer, providing a mold layer provided on the sacrificial layer, the redistribution wiring layer, and the plurality of semiconductor chips, detaching the first sacrificial layer from the second sacrificial layer, and dicing the second sacrificial layer, the redistribution wiring layer, and the mold layer, wherein a diameters of the first sacrificial layer and the second sacrificial layer are respectively less than a diameter of the carrier substrate, and a diameter of the mold layer is greater than the diameter of the redistribution wiring layer and less than the diameter of the first sacrificial layer.

公开(公告)号：US12230556B2

公开(公告)日：2025-02-18

申请号：US18588699

申请日：2024-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongyoun Kim ,  Minjun Bae ,  Hyeonseok Lee ,  Gwangjae Jeon

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/18 ,  H01L23/34

Abstract: Disclosed are semiconductor packages and their fabricating methods. The semiconductor package comprises a redistribution substrate, a semiconductor chip on a top surface of the redistribution substrate, and a solder terminal on a bottom surface of the redistribution substrate. The redistribution substrate includes an under-bump pattern in contact with the solder terminal, a dielectric layer on a sidewall of the under-bump pattern, an under-bump seed pattern between the dielectric layer and the sidewall of the under-bump pattern, and a redistribution pattern on the under-bump pattern. The under-bump pattern has central and edge regions. A first top surface at the edge region of the under-bump pattern is at a level higher than that of a second top surface at the central region of the under-bump pattern. An angle between the bottom surface and the sidewall of the under-bump pattern is in a range of 110° to 140°.

公开(公告)号：US20240096831A1

公开(公告)日：2024-03-21

申请号：US18455943

申请日：2023-08-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Enbin Jo ,  Hyungchul Shin ,  Wonil Lee ,  Hyuekjae Lee ,  Gwangjae Jeon

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/08 ,  H01L25/0657 ,  H01L24/16 ,  H01L2224/0801 ,  H01L2224/08058 ,  H01L2224/08146 ,  H01L2224/16227 ,  H01L2225/06541 ,  H01L2924/37

Abstract: A semiconductor package includes: a first semiconductor chip including a first pad on a first substrate, and a first insulating layer at least partially surrounding the first pad; and a second semiconductor chip including a second pad below a second substrate and contacting the first pad, and a second insulating layer at least partially surrounding the second pad and contacting the first insulating layer. The first pad includes a first surface contacting the second pad and a second surface opposite the first surface, and an inclined side surface between the first surface and the second surface. The inclined side surface includes a first side surface and a second side surface, facing each other and inclined at a first obtuse angle and a second obtuse angle with respect to the second surface, respectively. Each of the first and second obtuse angles is about 100° to about 130°.

公开(公告)号：US11804427B2

公开(公告)日：2023-10-31

申请号：US17177305

申请日：2021-02-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongkyu Kim ,  Seokhyun Lee ,  Kyoung Lim Suk ,  Jaegwon Jang ,  Gwangjae Jeon

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/49822 ,  H01L23/49833 ,  H01L23/49894 ,  H01L24/16 ,  H01L24/32 ,  H01L25/0657 ,  H01L2224/16227 ,  H01L2224/32225

Abstract: A semiconductor package may include a redistribution substrate, a connection terminal, and a semiconductor chip sequentially stacked. The redistribution substrate may include an insulating layer, a plurality of redistribution patterns, which are vertically stacked in the insulating layer, and each of which includes interconnection and via portions, and a bonding pad on the interconnection portion of the topmost redistribution pattern. The topmost redistribution pattern and the bonding pad may include different metallic materials. The bonding pad may have first and second surfaces opposite to each other. The first surface of the bonding pad may be in contact with a top surface of the interconnection portion of the topmost redistribution pattern. A portion of the second surface of the bonding pad may be in contact with the connection terminal. The insulating layer may be extended to be in contact with the remaining portion of the second surface.

公开(公告)号：US20240413026A1

公开(公告)日：2024-12-12

申请号：US18658546

申请日：2024-05-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeongbeom KO ,  Seokgeun Ahn ,  Juhyeon Oh ,  Sanghoon Lee ,  Gwangjae Jeon

IPC: H01L23/13 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065 ,  H10B80/00

Abstract: A semiconductor package includes a buffer die, a plurality of core die blocks sequentially stacked on the buffer die, and a molding member on the buffer die and covering outer surfaces of the plurality of core die blocks. Each of the plurality of core die blocks includes a first semiconductor chip, a second semiconductor chip disposed on the first semiconductor chip and a first gap filling portion, a third semiconductor chip disposed on the second semiconductor chip and a second gap filling portion, and a fourth semiconductor chip disposed on the third semiconductor chip.

公开(公告)号：US11948872B2

公开(公告)日：2024-04-02

申请号：US17509224

申请日：2021-10-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongyoun Kim ,  Minjun Bae ,  Hyeonseok Lee ,  Gwangjae Jeon

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/18 ,  H01L23/34

CPC classification number: H01L23/49811 ,  H01L23/3128 ,  H01L23/49822 ,  H01L24/16 ,  H01L25/18 ,  H01L23/34 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/73204

Abstract: Disclosed are semiconductor packages and their fabricating methods. The semiconductor package comprises a redistribution substrate, a semiconductor chip on a top surface of the redistribution substrate, and a solder terminal on a bottom surface of the redistribution substrate. The redistribution substrate includes an under-bump pattern in contact with the solder terminal, a dielectric layer on a sidewall of the under-bump pattern, an under-bump seed pattern between the dielectric layer and the sidewall of the under-bump pattern, and a redistribution pattern on the under-bump pattern. The under-bump pattern has central and edge regions. A first top surface at the edge region of the under-bump pattern is at a level higher than that of a second top surface at the central region of the under-bump pattern. An angle between the bottom surface and the sidewall of the under-bump pattern is in a range of 110° to 140°.