Abstract:
Provided are a fluorinated compound for patterning a metal or an electrode (cathode), an organic electronic element using the same, and an electronic device thereof, wherein a fine pattern of the electrode is formed by using the fluorinated compound as a material for patterning a metal or an electrode (cathode), without using a shadow mask, and it is possible to more easily apply UDC since it is easy to manufacture a transparent display having high light transmittance.
Abstract:
Provided are a fluorinated compound for patterning a metal or an electrode (cathode), an organic electronic element using the same, and an electronic device thereof, wherein a fine pattern of the electrode is formed by using the fluorinated compound as a material for patterning a metal or an electrode (cathode), without using a shadow mask, and it is possible to more easily apply UDC since it is easy to manufacture a transparent display having high light transmittance.
Abstract:
A thin film transistor array panel includes a gate line disposed on a substrate, the gate line including a gate electrode, a gate insulating layer disposed on the gate electrode, a semiconductor layer disposed on the substrate, the semiconductor layer including an oxide semiconductor, a data line disposed on the substrate and crossing the gate line, a data line layer including a source electrode connected to the data line and a drain electrode facing the source electrode, and a passivation layer covering the source electrode and the drain electrode. The data line layer includes copper or a copper alloy, and the semiconductor layer includes a copper doped oxide semiconductor. A content of copper doped on the oxide semiconductor is 0.2% to 0.82%.
Abstract:
A thin film transistor array panel according to an exemplary embodiment of the present invention includes: a substrate; a gate line positioned on the substrate; a gate insulating layer positioned on the gate line; a semiconductor layer positioned on the gate insulating layer and having a channel portion; a data line including a source electrode and a drain electrode, the source and drain electrodes both positioned on the semiconductor layer; a passivation layer positioned on the data line and the drain electrode and having a contact hole formed therein; and a pixel electrode positioned on the passivation layer, wherein the pixel electrode contacts the drain electrode within the contact hole, and the channel portion of the semiconductor layer and the contact hole both overlap the gate line in a plan view of the substrate.