公开(公告)号：US20240162180A1

公开(公告)日：2024-05-16

申请号：US18413887

申请日：2024-01-16

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Feng Kao ,  Lung-Yuan Wang

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L24/17 ,  H01L21/56 ,  H01L23/3157 ,  H01L24/13 ,  H01L24/16 ,  H01L24/24 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L2224/13005 ,  H01L2224/13083 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2224/24227 ,  H01L2224/73209 ,  H01L2224/92124

Abstract: An electronic package is provided, which stacks an electronic structure as an integrated voltage regulator on an electronic component to facilitate close-range cooperation with the electronic component for electrical transmission.

公开(公告)号：US11984393B2

公开(公告)日：2024-05-14

申请号：US17101277

申请日：2020-11-23

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Feng Kao ,  Lung-Yuan Wang

IPC: H01L21/768 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/495 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L25/065

CPC classification number: H01L23/5226 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/563 ,  H01L23/31 ,  H01L24/14

Abstract: An electronic package is provided, in which an electronic structure used as an integrated voltage regulator and a plurality of conductive pillars are embedded in an encapsulating layer to facilitate electrical transmission with electronic components at a close range.

公开(公告)号：US20170207104A1

公开(公告)日：2017-07-20

申请号：US15478508

申请日：2017-04-04

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Cheng-Chia Chiang ,  Don-Son Jiang ,  Lung-Yuan Wang ,  Shih-Hao Tung ,  Shu-Huei Huang

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L21/48 ,  H01L23/31

CPC classification number: H01L21/563 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/05647 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2924/14 ,  H01L2924/18161 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/014

Abstract: A semiconductor package is provided, which includes: a packaging substrate having opposite first and second surfaces and a plurality of first and second conductive pads formed on the first surface; a chip having opposite active and inactive surfaces and disposed on the first conductive pads via the active surface thereof; a plurality of conductive posts formed on the second conductive pads, respectively; and a first encapsulant formed on the first surface of the packaging substrate for encapsulating the chip and the conductive posts and having a plurality of openings for exposing upper surfaces of the conductive posts, thereby increasing the package density and protecting the chip and the interconnection structure from being adversely affected by intrusion of moisture.

公开(公告)号：US20150255360A1

公开(公告)日：2015-09-10

申请号：US14452871

申请日：2014-08-06

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chu-Chi Hsu ,  Lung-Yuan Wang ,  Cheng-Chia Chiang ,  Chia-Kai Shih ,  Shu-Huei Huang

IPC: H01L23/31 ,  H01L25/10 ,  H01L23/00

CPC classification number: H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13186 ,  H01L2224/16168 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/92125 ,  H01L2225/06517 ,  H01L2225/1017 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19102 ,  H01L2924/19103 ,  H01L2924/3511 ,  H01L2924/37001 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A package on package (PoP) structure is provided, which includes: a packaging substrate having a plurality of conductive bumps, wherein each of the conductive bumps has a metal ball and a solder material covering the metal ball; and an electronic element having a plurality of conductive posts, wherein the electronic element is stacked on the packaging substrate by correspondingly bonding the conductive posts to the conductive bumps, and each of the conductive posts and the corresponding conductive bump form a conductive element. The present invention facilitates the stacking process through butt joint of the conductive posts and the metal balls of the conductive bumps.

Abstract translation: 提供一种封装封装（PoP）结构，其包括：具有多个导电凸块的封装基板，其中每个导电凸块具有覆盖金属球的金属球和焊料; 以及具有多个导电柱的电子元件，其中通过将导电柱相应地接合到导电凸块上，电子元件堆叠在封装衬底上，并且每个导电柱和相应的导电凸块形成导电元件。 本发明有助于通过导电柱和导电凸块的金属球的对接的堆叠过程。

公开(公告)号：US20240379534A1

公开(公告)日：2024-11-14

申请号：US18623879

申请日：2024-04-01

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Feng Kao ,  Lung-Yuan Wang

IPC: H01L23/522 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

Abstract: An electronic package is provided, in which an electronic structure used as an integrated voltage regulator and a plurality of conductive pillars are embedded in an encapsulating layer to facilitate electrical transmission with electronic components at a close range.

公开(公告)号：US12009340B2

公开(公告)日：2024-06-11

申请号：US17481610

申请日：2021-09-22

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Lung-Yuan Wang ,  Feng Kao ,  Mao-Hua Yeh

IPC: H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L23/552 ,  H01L25/00 ,  H01L25/16

CPC classification number: H01L25/0652 ,  H01L21/4853 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/552 ,  H01L25/16 ,  H01L25/50

Abstract: An electronic package and a method for fabricating the same are provided. Two packaging modules are stacked on each other. An area that an electronic package occupies a mother board is reduced during a subsequent process of fabricating an electronic product. Therefore, the electronic product has a reduced size.

公开(公告)号：US11973047B2

公开(公告)日：2024-04-30

申请号：US17102841

申请日：2020-11-24

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Feng Kao ,  Lung-Yuan Wang

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L24/17 ,  H01L21/56 ,  H01L23/3157 ,  H01L24/13 ,  H01L24/16 ,  H01L24/24 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L2224/13005 ,  H01L2224/13083 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2224/24227 ,  H01L2224/73209 ,  H01L2224/92124

Abstract: An electronic package is provided, which stacks an electronic structure as an integrated voltage regulator on an electronic component to facilitate close-range cooperation with the electronic component for electrical transmission.

公开(公告)号：US20230260886A1

公开(公告)日：2023-08-17

申请号：US17726163

申请日：2022-04-21

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Feng Kao ,  Lung-Yuan Wang

IPC: H01L23/498 ,  H01L23/367 ,  H01L21/48 ,  H01L23/14

CPC classification number: H01L23/49833 ,  H01L21/4857 ,  H01L23/145 ,  H01L23/3675 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L25/0655

Abstract: An electronic package is provided, in which a circuit structure is disposed on the uppermost side of a plurality of stacked organic material substrates for connecting an electronic element, so that a line width/line spacing of a redistribution layer of the circuit structure conforms with a line width/line spacing of the electronic element. Therefore, when the size specification of the electronic element is designed to be miniaturized, the redistribution layer configured in the circuit structure can effectively match the line spacing/line width of the electronic element, so as to meet the requirements of miniaturized packaging.

公开(公告)号：US20210051800A1

公开(公告)日：2021-02-18

申请号：US16589663

申请日：2019-10-01

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Lung-Yuan Wang ,  Wen-Liang Lien

IPC: H05K1/14 ,  H05K1/18 ,  H05K3/32 ,  H01L23/31

Abstract: A method for fabricating an assemble substrate is provided, including stacking a circuit portion on a plurality of circuit members. The circuit members are spaced apart from one another in a current packaging process to increase a layer area. The assemble substrate thus fabricated meets the requirements for a packaging substrate of a large size, and has a high yield and low fabrication cost.

公开(公告)号：US20150123287A1

公开(公告)日：2015-05-07

申请号：US14133868

申请日：2013-12-19

Applicant: Siliconware Precision Industries Co., Ltd

Inventor： Chu-Chi Hsu ,  Lung-Yuan Wang ,  Cheng-Chia Chiang ,  Chia-Kai Shih

IPC: H01L25/065 ,  H01L21/02 ,  H01L25/00 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L21/02057 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/562 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/85005 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/15162 ,  H01L2924/15174 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  Y10T428/192 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method for fabricating a semiconductor package is disclosed, which includes the steps of: providing a first substrate; disposing a second substrate on the first substrate through a plurality of supporting elements, wherein the second substrate has at least a cleaning hole penetrating therethrough; and performing a cleaning process to clean space between the second substrate and the first substrate through the cleaning hole, thereby preventing a popcorn effect from occurring when the first substrate is heated and hence preventing delamination of the semiconductor package. Further, the cleaning hole facilitates to disperse thermal stresses so as to prevent warping of the first and second substrates during a chip-bonding or encapsulating process, thereby overcoming the conventional drawbacks of cracking of the supporting elements and a short circuit therebetween.

Abstract translation: 公开了一种制造半导体封装的方法，其包括以下步骤：提供第一衬底; 通过多个支撑元件将第二基板设置在第一基板上，其中第二基板至少具有贯穿其中的清洁孔; 并且通过清洁孔进行清洁处理以清洁第二基板和第一基板之间的空间，从而防止当第一基板被加热时出现爆米花效应，从而防止半导体封装的分层。 此外，清洁孔有利于分散热应力，以防止在芯片接合或封装过程中第一和第二基板的翘曲，从而克服了支撑元件的破裂和它们之间的短路的常规缺点。