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    SUBSTRATE ALIGNMENT SYSTEMS AND RELATED METHODS
    3.
    发明申请
    SUBSTRATE ALIGNMENT SYSTEMS AND RELATED METHODS 审中-公开

    公开(公告)号：US20200243366A1

    公开(公告)日：2020-07-30

    申请号：US16505949

    申请日：2019-07-09

    申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    发明人： Michael J. SEDDON ,  Takashi NOMA

    IPC分类号： H01L21/68 ,  H01L21/78 ,  H01L23/544

    摘要： Implementations of a method of making a plurality of alignment marks on a wafer may include: providing a wafer including an alignment feature on a first side of the wafer. The method may include aligning the wafer using a camera focused on the first side of the wafer. The wafer may be aligned using the alignment feature on the first side of the die. The wafer may also include creating a plurality of alignment marks on a second side of the wafer through lasering, sawing, or scribing.

    THINNED SEMICONDUCTOR PACKAGE AND RELATED METHODS
    4.
    发明申请
    THINNED SEMICONDUCTOR PACKAGE AND RELATED METHODS 审中-公开

    公开(公告)号：US20190287913A1

    公开(公告)日：2019-09-19

    申请号：US15921898

    申请日：2018-03-15

    申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    发明人： Yusheng LIN ,  Takashi NOMA ,  Francis J. CARNEY

    IPC分类号： H01L23/532 ,  H01L23/00

    摘要： Implementations of semiconductor packages may include a die having a first side and a second side opposite the first side, a first metal layer coupled to the first side of the die, a tin layer coupled to the first metal layer, the first metal layer between the die and the tin layer, a backside metal layer coupled to the second side of the die, and a mold compound coupled to the die. The mold compound may cover a plurality of sidewalls of the first metal layer and a plurality of sidewalls of the tin layer and a surface of the mold compound is coplanar with a surface of the tin layer.

    MULTI-CHIP SYSTEM-IN-PACKAGE
    6.
    发明申请
    MULTI-CHIP SYSTEM-IN-PACKAGE 有权

    公开(公告)号：US20220359360A1

    公开(公告)日：2022-11-10

    申请号：US17661420

    申请日：2022-04-29

    申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    发明人： Yusheng LIN ,  Takashi NOMA

    IPC分类号： H01L23/498 ,  H01L25/065 ,  H01L23/48 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L21/768 ,  H01L25/00

    摘要： A system-in-package includes an interposer substrate having a first side and a second side opposite the first side, and a redistribution layer disposed on the first side. The redistribution layer includes a plurality of contact pads and a plurality of interconnections disposed on the first side. The plurality of interconnections is electrically connected to a plurality of terminals disposed on the second side opposite the first side. A first semiconductor die is disposed on the first side and electrically coupled to a first of the plurality of contact pads and a first of the plurality of interconnections disposed on the first side of the interposer substrate. A second semiconductor die is disposed on the first side. The second semiconductor die is electrically coupled to a second of the plurality of contact pads and a second of the plurality of interconnections disposed on the first side of the interposer substrate.

    METHODS OF ALIGNING A SEMICONDUCTOR WAFER FOR SINGULATION
    8.
    发明申请
    METHODS OF ALIGNING A SEMICONDUCTOR WAFER FOR SINGULATION 有权

    公开(公告)号：US20220172994A1

    公开(公告)日：2022-06-02

    申请号：US17651610

    申请日：2022-02-18

    申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    发明人： Michael J. SEDDON ,  Takashi NOMA

    IPC分类号： H01L21/78 ,  H01L21/66 ,  H01L21/3205 ,  H01L21/683 ,  H01L21/02 ,  H01L21/304

    摘要： Implementations of a method for aligning a semiconductor wafer for singulation may include: providing a semiconductor wafer having a first side and a second side. The first side of the wafer may include a plurality of die and the plurality of die may be separated by streets. The semiconductor wafer may include an edge ring around a perimeter of the wafer on the second side of the wafer. The wafer may also include a metal layer on the second side of the wafer. The metal layer may substantially cover the edge ring. The method may include grinding the edge ring to create an edge exclusion area and aligning the semiconductor wafer with a saw using a camera positioned in the edge exclusion area on the second side of the wafer. Aligning the wafer may include using three or more alignment features included in the edge exclusion area.

    FAN-OUT WAFER LEVEL PACKAGING OF SEMICONDUCTOR DEVICES
    9.
    发明申请
    FAN-OUT WAFER LEVEL PACKAGING OF SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20210305096A1

    公开(公告)日：2021-09-30

    申请号：US17304136

    申请日：2021-06-15

    申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    发明人： George CHANG ,  Yusheng LIN ,  Gordon M. GRIVNA ,  Takashi NOMA

    IPC分类号： H01L21/78 ,  H01L21/683 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00

    摘要： In a general aspect, a fan-out wafer level package (FOWLP) can include a semiconductor die having an active surface, a backside surface, a plurality of side surfaces, each side surface of the plurality of side surfaces extending between the active surface and the backside surface, a plurality of conductive bumps disposed on the active surface, and an insulating layer disposed on a first portion of the active surface between the conductive bumps. The FOWLP can also include a molding compound encapsulating the backside surface, the plurality of side surfaces, and a second portion of the active surface between the conductive bumps and a perimeter edge of the active surface. The FOWLP can also include a signal distribution structure disposed on the conductive bumps, the insulating layer and the molding compound. The signal distribution structure can be configured to provide respective electrical connections to the plurality of conductive bumps.