公开(公告)号：US20140252544A1

公开(公告)日：2014-09-11

申请号：US13785502

申请日：2013-03-05

Applicant: QUALCOMM INCORPORATED

Inventor： Yue Li ,  Xiaoming Chen ,  Zhongping Bao ,  Charles D. Paynter ,  Xiaonan Zhang ,  Ryan D. Lane

IPC: H01L49/02

CPC classification number: H01G2/06 ,  H01G4/38 ,  H01G4/40 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/642 ,  H01L24/17 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Some implementations provide a semiconductor device that includes a first substrate, a die coupled to the first substrate, and a set of solder balls coupled to the first substrate. The set of solder balls is configured to provide an electrical connection between the die and a second substrate. The semiconductor device also includes at least one decoupling capacitor coupled to the die through the first substrate. The at least one decoupling capacitor is configured to provide an electrical connection between the die and the second substrate. The at least one decoupling capacitor is coupled to the first substrate such that the at least one decoupling capacitor is positioned between the first substrate and the second substrate. In some implementations, the second substrate is a printed circuit board (PCB). In some implementations, the first substrate is a first package substrate, and the second substrate is a second package substrate.

Abstract translation: 一些实施方式提供一种半导体器件，其包括第一衬底，耦合到第一衬底的管芯和耦合到第一衬底的一组焊球。 该组焊球被配置成在管芯和第二衬底之间提供电连接。 半导体器件还包括通过第一衬底耦合到管芯的至少一个去耦电容器。 所述至少一个去耦电容器被配置为在所述管芯和所述第二衬底之间提供电连接。 所述至少一个去耦电容器耦合到所述第一衬底，使得所述至少一个去耦电容器位于所述第一衬底和所述第二衬底之间。 在一些实施方案中，第二衬底是印刷电路板（PCB）。 在一些实施方案中，第一衬底是第一封装衬底，第二衬底是第二封装衬底。

公开(公告)号：US20140246753A1

公开(公告)日：2014-09-04

申请号：US13787219

申请日：2013-03-06

Applicant: QUALCOMM INCORPORATED

Inventor： Young K. Song ,  Yunseo Park ,  Xiaonan Zhang ,  Ryan D. Lane ,  Babak Nejati ,  Aristotele Hadjichristos ,  Xiaoming Chen

IPC: H01L23/522 ,  H01L23/00

CPC classification number: H01L23/5227 ,  H01L23/645 ,  H01L24/02 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/117 ,  H01L2224/02375 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2225/06513 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15331 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/00012

Abstract: Some novel features pertain to a first example provides a semiconductor device that includes a printed circuit board (PCB), asset of solder balls and a die. The PCB includes a first metal layer. The set of solder balls is coupled to the PCB. The die is coupled to the PCB through the set of solder balls. The die includes a second metal layer and a third metal layer. The first metal layer of the PCB, the set of solder balls, the second and third metal layers of the die are configured to operate as an inductor in the semiconductor device. In some implementations, the die further includes a passivation layer. The passivation layer is positioned between the second metal layer and the third metal layer. In some implementations, the second metal layer is positioned between the passivation layer and the set of solder balls.

Abstract translation: 一些新颖特征涉及第一示例，提供了包括印刷电路板（PCB），焊球和裸片的资产的半导体器件。 PCB包括第一金属层。 该组焊球与PCB相连。 模具通过一组焊球耦合到PCB。 模具包括第二金属层和第三金属层。 PCB的第一金属层，焊球集合，管芯的第二和第三金属层被配置为在半导体器件中作为电感器工作。 在一些实施方式中，芯片还包括钝化层。 钝化层位于第二金属层和第三金属层之间。 在一些实施方案中，第二金属层位于钝化层和一组焊球之间。

公开(公告)号：US09035421B2

公开(公告)日：2015-05-19

申请号：US13787219

申请日：2013-03-06

Applicant: QUALCOMM Incorporated

Inventor： Young K. Song ,  Yunseo Park ,  Xiaonan Zhang ,  Ryan D. Lane ,  Babak Nejati ,  Aristotele Hadjichristos ,  Xiaoming Chen

IPC: H01L27/08 ,  H01L23/522 ,  H01L23/00 ,  H01L23/64 ,  H01L25/065 ,  H01L25/07 ,  H01L25/11

CPC classification number: H01L23/5227 ,  H01L23/645 ,  H01L24/02 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/117 ,  H01L2224/02375 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2225/06513 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15331 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/00012

Abstract: Some novel features pertain to a first example provides a semiconductor device that includes a printed circuit board (PCB), asset of solder balls and a die. The PCB includes a first metal layer. The set of solder balls is coupled to the PCB. The die is coupled to the PCB through the set of solder balls. The die includes a second metal layer and a third metal layer. The first metal layer of the PCB, the set of solder balls, the second and third metal layers of the die are configured to operate as an inductor in the semiconductor device. In some implementations, the die further includes a passivation layer. The passivation layer is positioned between the second metal layer and the third metal layer. In some implementations, the second metal layer is positioned between the passivation layer and the set of solder balls.

Abstract translation: 一些新颖特征涉及第一示例，提供了包括印刷电路板（PCB），焊球和裸片的资产的半导体器件。 PCB包括第一金属层。 该组焊球与PCB相连。 模具通过一组焊球耦合到PCB。 模具包括第二金属层和第三金属层。 PCB的第一金属层，焊球集合，管芯的第二和第三金属层被配置为在半导体器件中作为电感器工作。 在一些实施方式中，芯片还包括钝化层。 钝化层位于第二金属层和第三金属层之间。 在一些实施方案中，第二金属层位于钝化层和一组焊球之间。

公开(公告)号：US11406006B2

公开(公告)日：2022-08-02

申请号：US17122820

申请日：2020-12-15

Applicant: QUALCOMM Incorporated

Inventor： Xiaoming Chen ,  Darryl Sheldon Jessie

IPC: H05K1/02 ,  H05K1/11

Abstract: Certain aspects of the present disclosure generally relate to a circuit board with ground vias offset from associated ground bumps. One example circuit board generally includes a first signal connection terminal configured to connect a signal line of the circuit board to an integrated circuit (IC); a ground plane having a first ground connection terminal disposed adjacent to the first signal connection terminal, the first ground connection terminal being configured to provide a ground connection between the ground plane and the IC; and a first ground via associated with and disposed adjacent to the first ground connection terminal and coupled to the ground plane, wherein, from an overhead view of the circuit board, the first ground via is located at a position that is offset from a first axis on which the first signal connection terminal and the first ground connection terminal are disposed.

公开(公告)号：US11139224B2

公开(公告)日：2021-10-05

申请号：US16704789

申请日：2019-12-05

Applicant: QUALCOMM Incorporated

Inventor： Chaoqi Zhang ,  Rajneesh Kumar ,  Li-Sheng Weng ,  Darryl Sheldon Jessie ,  Suhyung Hwang ,  Jeahyeong Han ,  Xiaoming Chen ,  Jaehyun Yeon

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/56 ,  H01L21/67 ,  H01L23/31

Abstract: A package that includes a substrate having a routing region and a non-routing region along a periphery of the substrate. The non-routing region includes a plurality of vias configured as a shield. The package includes an integrated device coupled to the substrate, and an encapsulation layer located over the substrate such that the encapsulation layer encapsulates the integrated device.

公开(公告)号：US09263186B2

公开(公告)日：2016-02-16

申请号：US13785502

申请日：2013-03-05

Applicant: QUALCOMM Incorporated

Inventor： Yue Li ,  Xiaoming Chen ,  Zhongping Bao ,  Charles D. Paynter ,  Xiaonan Zhang ,  Ryan D. Lane

IPC: H01L49/02 ,  H01G2/06 ,  H01L23/50 ,  H01L23/64 ,  H01L23/00 ,  H01G4/38 ,  H01G4/40 ,  H01L23/498

CPC classification number: H01G2/06 ,  H01G4/38 ,  H01G4/40 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/642 ,  H01L24/17 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Some implementations provide a semiconductor device that includes a first substrate, a die coupled to the first substrate, and a set of solder balls coupled to the first substrate. The set of solder balls is configured to provide an electrical connection between the die and a second substrate. The semiconductor device also includes at least one decoupling capacitor coupled to the die through the first substrate. The at least one decoupling capacitor is configured to provide an electrical connection between the die and the second substrate. The at least one decoupling capacitor is coupled to the first substrate such that the at least one decoupling capacitor is positioned between the first substrate and the second substrate. In some implementations, the second substrate is a printed circuit board (PCB). In some implementations, the first substrate is a first package substrate, and the second substrate is a second package substrate.

Abstract translation: 一些实施方式提供一种半导体器件，其包括第一衬底，耦合到第一衬底的管芯和耦合到第一衬底的一组焊球。 该组焊球被配置成在管芯和第二衬底之间提供电连接。 半导体器件还包括通过第一衬底耦合到管芯的至少一个去耦电容器。 所述至少一个去耦电容器被配置为在所述管芯和所述第二衬底之间提供电连接。 所述至少一个去耦电容器耦合到所述第一衬底，使得所述至少一个去耦电容器位于所述第一衬底和所述第二衬底之间。 在一些实施方案中，第二衬底是印刷电路板（PCB）。 在一些实施方案中，第一衬底是第一封装衬底，第二衬底是第二封装衬底。