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    MAGNETRESISTIVE RANDOM-ACCESS MEMORY AND FABRICATION METHOD THEREOF
    1.
    发明申请
    MAGNETRESISTIVE RANDOM-ACCESS MEMORY AND FABRICATION METHOD THEREOF 审中-公开

    公开(公告)号：US20170084819A1

    公开(公告)日：2017-03-23

    申请号：US14859278

    申请日：2015-09-19

    Applicant: QUALCOMM Incorporated

    Inventor： Yu LU ,  Wei-Chuan CHEN ,  Seung Hyuk KANG

    IPC: H01L43/02 ,  H01L43/12 ,  H01L43/08

    CPC classification number: H01L43/12 ,  H01L27/222 ,  H01L43/08

    Abstract: Provided are exemplary circuits including a magnetoresistive random-access memory (MRAM) and methods for fabricating the circuits. In an example, a circuit includes an MRAM. The circuit includes a bottom interconnect in a bottom interconnect level. The bottom interconnect is configured to route a signal outside of a magnetic tunnel junction (MTJ) stack. The circuit includes the MTJ stack formed on a bottom electrode at least partially embedded in the bottom interconnect level. Optionally, the circuit also includes an encapsulation layer encapsulating at least a portion of the MTJ stack. The encapsulation layer is also an electromigration cap for a second bottom interconnect in the bottom interconnect level. The second bottom interconnect is a not part of the MTJ stack. Optionally, the bottom electrode is self-aligned with the bottom interconnect.

    EMBEDDED MAGNETORESISTIVE RANDOM ACCESS MEMORY (MRAM) INTEGRATION WITH TOP CONTACTS
    2.
    发明申请
    EMBEDDED MAGNETORESISTIVE RANDOM ACCESS MEMORY (MRAM) INTEGRATION WITH TOP CONTACTS 有权
    嵌入式磁阻随机访问存储器（MRAM）与顶级联系人集成

    公开(公告)号：US20160133828A1

    公开(公告)日：2016-05-12

    申请号：US14625494

    申请日：2015-02-18

    Applicant: QUALCOMM Incorporated

    Inventor： Yu LU ,  Wei-Chuan CHEN ,  Seung Hyuk KANG

    IPC: H01L43/08 ,  H01L43/12 ,  H01L43/02

    CPC classification number: H01L43/08 ,  H01L27/222 ,  H01L43/02 ,  H01L43/12

    Abstract: A magnetoresistive random access memory (MRAM) device includes a top electrode or top contact above a metal hard mask which has a limited height due to process limitations in advanced nodes. The metal hard mask is provided on a magnetic tunnel junction (MTJ). The top contact for the MTJ is formed within a dielectric layer, such as a low dielectric constant (low-k) or extremely low-k layer. An additional dielectric layer is provided above the top contact for additional connections for additional circuitry to form a three-dimensional integrated circuit (3D IC).

    Abstract translation: 磁阻随机存取存储器（MRAM）装置包括金属硬掩模上方的顶部电极或顶部触点，由于先进节点中的工艺限制，其具有有限的高度。 金属硬掩模设置在磁性隧道结（MTJ）上。 MTJ的顶部接触形成在介电层内，例如低介电常数（低k）或极低k层。 在顶部触点上方提供了另外的介电层，用于额外的连接，用于附加电路以形成三维集成电路（3D IC）。

    REPLACEMENT CONDUCTIVE HARD MASK FOR MULTI-STEP MAGNETIC TUNNEL JUNCTION (MTJ) ETCH
    6.
    发明申请
    REPLACEMENT CONDUCTIVE HARD MASK FOR MULTI-STEP MAGNETIC TUNNEL JUNCTION (MTJ) ETCH 审中-公开

    公开(公告)号：US20160133833A1

    公开(公告)日：2016-05-12

    申请号：US14995193

    申请日：2016-01-13

    Applicant: QUALCOMM INCORPORATED

    Inventor： Yu LU ,  Chando PARK ,  Wei-Chuan CHEN

    IPC: H01L43/12 ,  H01L43/02 ,  H01L43/08

    CPC classification number: H01L43/12 ,  H01L43/02 ,  H01L43/08

    Abstract: A multi-step etch technique for fabricating a magnetic tunnel junction (MTJ) apparatus includes forming a first conductive hard mask on a first electrode of the MTJ apparatus for etching the first electrode during a first etching step. The method also includes forming a second conductive hard mask on the first conductive hard mask for etching magnetic layers of the MTJ apparatus during a second etching step. A spacer layer is conformally deposited on sidewalls of the first conductive hard mask. The second conductive hard mask is deposited on the first conductive hard mask and aligned with the spacer layer on the sidewalls of the first conductive hard mask.

    SPIN-TRANSFER SWITCHING MAGNETIC ELEMENT FORMED FROM FERRIMAGNETIC RARE-EARTH-TRANSITION-METAL (RE-TM) ALLOYS
    7.
    发明申请
    SPIN-TRANSFER SWITCHING MAGNETIC ELEMENT FORMED FROM FERRIMAGNETIC RARE-EARTH-TRANSITION-METAL (RE-TM) ALLOYS 审中-公开
    旋转转换金属（RE-TM）合金形成的转子切换磁性元件

    公开(公告)号：US20150303373A1

    公开(公告)日：2015-10-22

    申请号：US14255624

    申请日：2014-04-17

    Applicant: QUALCOMM Incorporated

    Inventor： Wei-Chuan CHEN ,  Xiaochun ZHU ,  Chando PARK ,  Seung Hyuk KANG

    IPC: H01L43/08 ,  H01L43/12 ,  H01L43/02 ,  H01L43/10

    CPC classification number: H01L43/08 ,  G11C11/161 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

    Abstract: A magnetic tunnel junction (MTJ) includes a free layer formed from a ferrimagnetic rare-earth-transition-metal (RE-TM) alloy having the net moment dominated by a sublattice moment of a rare-earth (RE) composition of the RE-TM alloy. The MTJ further includes a pinned layer formed from a rare-earth-transition-metal (RE-TM) alloy having the net moment dominated by a sublattice moment of a rare-earth (RE) composition of the RE-TM alloy, the pinned layer comprising one or more amorphous thin insertion layers such that a net magnetic moment of the free layer and the pinned layer is low or close to zero.

    Abstract translation: 磁隧道结（MTJ）包括由铁氧体稀土 - 过渡金属（RE-TM）合金形成的自由层，其具有由RE-稀土 - 过渡金属（RE-TM）合金的稀土（RE）组成的亚晶格矩所主导的净时刻， TM合金。 MTJ还包括由稀土 - 过渡金属（RE-TM）合金形成的钉扎层，其具有以RE-TM合金的稀土（RE）组合物的亚晶格矩为主的净矩，被钉扎 层包括一个或多个非晶薄插入层，使得自由层和钉扎层的净磁矩低或接近于零。

    DYNAMIC MEMORY PROTECTION
    9.
    发明申请
    DYNAMIC MEMORY PROTECTION 审中-公开

    公开(公告)号：US20190332306A1

    公开(公告)日：2019-10-31

    申请号：US15963668

    申请日：2018-04-26

    Applicant: QUALCOMM Incorporated

    Inventor： Chando PARK ,  Wei-Chuan CHEN ,  Sungryul KIM ,  Adam Edward NEWHAM ,  Seung Hyuk KANG ,  Rashid Ahmed Akbar ATTAR

    IPC: G06F3/06 ,  G11C11/00 ,  G11C29/52 ,  A61N1/372

    Abstract: Aspects of the present disclosure relate to protecting the contents of memory in an electronic device, and in particular to systems and methods for transferring data between memories of an electronic device in the presence of strong magnetic fields. In one embodiment, a method of protecting data in a memory in an electronic device includes storing data in a first memory in the electronic device; determining, via a magnetic sensor, a strength of an ambient magnetic field; comparing the strength of the ambient magnetic field to a threshold; transferring the data in the first memory to a second memory in the electronic device upon determining that the strength of the ambient magnetic field exceeds the threshold; and transferring the data from the second memory to the first memory upon determining that the strength of the ambient magnetic field no longer exceeds the threshold.

    DE-INTEGRATED TRENCH FORMATION FOR ADVANCED MRAM INTEGRATION
    10.
    发明申请
    DE-INTEGRATED TRENCH FORMATION FOR ADVANCED MRAM INTEGRATION 有权
    用于高级MRAM集成的集成化梯度形成

    公开(公告)号：US20160365505A1

    公开(公告)日：2016-12-15

    申请号：US14735006

    申请日：2015-06-09

    Applicant: QUALCOMM Incorporated

    Inventor： Yu LU ,  Wei-Chuan CHEN ,  Seung Hyuk KANG

    IPC: H01L43/02 ,  H01L43/10 ,  H01L27/22 ,  H01L43/08 ,  H01L43/12

    CPC classification number: H01L43/02 ,  H01L27/222 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

    Abstract: A semiconductor device may include a magnetoresistive random-access memory (MRAM) trench having a first conductive barrier liner and a second conductive barrier liner. The MRAM trench may land on a hard mask of a magnetic tunnel junction (MTJ) within an MTJ region of the semiconductor device. The semiconductor device may also include a logic trench having the first conductive barrier liner. The semiconductor device may further include a logic via having the first conductive barrier liner. The logic via may land on a first portion of a conductive interconnect (Mx) within a logic region of the semiconductor device.

    Abstract translation: 半导体器件可以包括具有第一导电阻挡衬垫和第二导电阻挡衬里的磁阻随机存取存储器（MRAM）沟槽。 MRAM沟槽可以落在半导体器件的MTJ区域内的磁性隧道结（MTJ）的硬掩模上。 半导体器件还可以包括具有第一导电阻挡衬里的逻辑沟槽。 半导体器件还可以包括具有第一导电阻挡衬里的逻辑通孔。 逻辑通孔可以落在半导体器件的逻辑区域内的导电互连（Mx）的第一部分上。

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