知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

9 records (took 0.016 seconds)

    Bulk cross-coupled high density power supply decoupling capacitor
    3.
    发明授权
    Bulk cross-coupled high density power supply decoupling capacitor 有权

    公开(公告)号：US10032763B2

    公开(公告)日：2018-07-24

    申请号：US15171987

    申请日：2016-06-02

    Applicant: QUALCOMM Incorporated

    Inventor： Albert Kumar ,  Hai Dang ,  Sreeker Dundigal ,  Vasisht Vadi

    IPC: H03K3/01 ,  H01L27/02 ,  H01L27/06 ,  H01L29/94 ,  H01L29/786 ,  H01L29/10

    Abstract: In an aspect of the disclosure, a MOS device for using bulk cross-coupled thin-oxide decoupling capacitor is provided. The MOS device may include a pMOS transistor and an nMOS transistor. The MOS device may include a first set of transistor body connections adjacent the pMOS transistor and the nMOS transistor. The first set of transistor body connections may couple a first voltage source to the pMOS transistor body. The first set of transistor body connections may further couple a second voltage source to the nMOS transistor body. The MOS device may include a second set of transistor body connections adjacent the pMOS transistor and the nMOS transistor. The second set of transistor body connections may couple the nMOS transistor gate to the pMOS transistor body. The second set of transistor body connections may further couple the pMOS transistor gate to the nMOS transistor body.

    Mixed mode RC clamps
    4.
    发明授权
    Mixed mode RC clamps 有权
    混合模式RC夹

    公开(公告)号：US09406627B2

    公开(公告)日：2016-08-02

    申请号：US14038663

    申请日：2013-09-26

    Applicant: QUALCOMM Incorporated

    Inventor： Eugene Robert Worley ,  Reza Jalilizeinali ,  Sreeker Dundigal

    IPC: H01L27/06 ,  H01L23/60 ,  H01L27/02 ,  H02H9/04

    CPC classification number: H01L23/60 ,  H01L27/0285 ,  H01L27/0682 ,  H01L2924/0002 ,  H02H9/046 ,  H01L2924/00

    Abstract: A system interconnect includes a first resistor-capacitor (RC) clamp having a first RC time constant. The system interconnect also includes second RC clamps having a second RC time constant. The first and second RC clamps are arranged along the system interconnect. In addition, the first RC time constant is different from the second RC time constant.

    Abstract translation: 系统互连包括具有第一RC时间常数的第一电阻器 - 电容（RC）钳位。 系统互连还包括具有第二RC时间常数的第二RC钳位。 第一和第二RC夹具沿着系统互连排列。 另外，第一RC时间常数与第二RC时间常数不同。

    ELECTROSTATIC DISCHARGE CIRCUIT WITH REDUCED STANDBY CURRENT
    5.
    发明申请
    ELECTROSTATIC DISCHARGE CIRCUIT WITH REDUCED STANDBY CURRENT 审中-公开
    具有降低待机电流的静电放电电路

    公开(公告)号：US20150249334A1

    公开(公告)日：2015-09-03

    申请号：US14194158

    申请日：2014-02-28

    Applicant: Qualcomm Incorporated

    Inventor： Wen-Yi Chen ,  Sreeker Dundigal ,  Reza Jalilizeinali ,  Eugene Robert Worley

    IPC: H02H9/04

    CPC classification number: H02H9/046

    Abstract: Techniques for reducing leakage current during normal operation of an electrostatic discharge (ESD) circuit are described herein. In one embodiment, a circuit comprises an internal circuit and an electrostatic discharge (ESD) rail clamp coupled in parallel to the internal circuit and between first and second power supply rails. The ESD rail clamp is operable to shunt ESD current from the first power supply rail to the second power supply rail via a low resistance shunt path. The ESD rail clamp comprises an ESD trigger circuit configured to detect an ESD event and a plurality of discharging transistors coupled in series. The ESD trigger circuit is configured to turn off the discharging transistors during normal operation and to turn on the discharging transistors to form the low resistance shunt path in response to detection of the ESD event.

    Abstract translation: 本文描述了用于在静电放电（ESD）电路的正常操作期间减小泄漏电流的技术。 在一个实施例中，电路包括与内部电路并联并且在第一和第二电源轨之间并联的内部电路和静电放电（ESD）导轨夹。 ESD导轨夹可用于通过低电阻分流路径将ESD电流从第一电源轨分流到第二电源轨。 ESD导轨夹具包括被配置为检测ESD事件的ESD触发电路和串联耦合的多个放电晶体管。 ESD触发电路被配置为在正常操作期间关闭放电晶体管，并且响应于ESD事件的检测而导通放电晶体管以形成低电阻分流路径。

    Interface circuit with robust electrostatic discharge
    6.
    发明授权
    Interface circuit with robust electrostatic discharge 有权

    公开(公告)号：US11575259B2

    公开(公告)日：2023-02-07

    申请号：US17370894

    申请日：2021-07-08

    Applicant: QUALCOMM Incorporated

    Inventor： Wen-Yi Chen ,  Reza Jalilizeinali ,  Sreeker Dundigal ,  Krishna Chaitanya Chillara ,  Gregory Lynch

    IPC: H02H9/04 ,  H01L27/02

    Abstract: An ESD protection circuit has a driver transistor with a drain that is coupled to an I/O pad of an IC device and a source that is coupled to a first rail of a power supply in the IC device, and a diode that couples the I/O pad to the first rail and that is configured to be reverse-biased when a rated voltage is applied to the I/O pad. The rated voltage lies within a nominal operating range for voltage levels defined for the input/output pad. The ESD protection circuit has a gate pull transistor that couples a gate of the driver transistor to the I/O pad or the first rail. The gate pull transistor may be configured to present a high impedance path between the gate of the driver transistor and the I/O pad or the first rail when the rated voltage is applied to the I/O pad. The gate pull transistor may be configured to provide a low impedance path between the gate of the driver transistor and the I/O pad or the first rail when an overvoltage signal applied to the I/O pad has a magnitude that exceeds the nominal operating range of voltage levels defined for the I/O pad.

    Electrostatic discharge clamp with disable
    8.
    发明授权
    Electrostatic discharge clamp with disable 有权
    带静电放电钳

    公开(公告)号：US09083176B2

    公开(公告)日：2015-07-14

    申请号：US13740102

    申请日：2013-01-11

    Applicant: QUALCOMM Incorporated

    Inventor： Eugene Robert Worley ,  Sreeker Dundigal ,  Evan Siansuri ,  Reza Jalilizeinali ,  Michael Brunolli

    IPC: H02H9/00 ,  H02H9/04 ,  G06F1/30 ,  H01L23/62

    CPC classification number: H02H9/046 ,  G06F1/305 ,  H01L23/62 ,  H01L2924/0002 ,  H02H9/043 ,  H01L2924/00

    Abstract: In a particular embodiment, a circuit includes a power supply, a ground, and a clamping transistor circuit coupled to the power supply and to the ground. The circuit further includes a disable clamp circuit. The disable clamp circuit is coupled to the power supply and is responsive to a second power supply input to selectively disable the clamping transistor circuit by modifying a charging current applied to a capacitor of the clamping transistor circuit. In a particular embodiment, modifying the charging current includes enabling a second charging path. Enabling the second charging path enables charging the capacitor at a higher charging rate than a charging rate associated with charging the capacitor via a first charging path.

    Abstract translation: 在特定实施例中，电路包括耦合到电源和接地的电源，接地和钳位晶体管电路。 电路还包括禁止钳位电路。 禁止钳位电路耦合到电源，并且响应于第二电源输入，以通过修改施加到钳位晶体管电路的电容器的充电电流来选择性地禁止钳位晶体管电路。 在特定实施例中，修改充电电流包括实现第二充电路径。 启用第二充电路径使得能够以比通过第一充电路径对电容器充电相关的充电速率更高的充电速率对电容器进行充电。

    ELECTROSTATIC DISCHARGE CLAMP WITH DISABLE
    9.
    发明申请
    ELECTROSTATIC DISCHARGE CLAMP WITH DISABLE 有权
    静电放电钳

    公开(公告)号：US20140198414A1

    公开(公告)日：2014-07-17

    申请号：US13740102

    申请日：2013-01-11

    Applicant: QUALCOMM INCORPORATED

    Inventor： Eugene Robert Worley ,  Sreeker Dundigal ,  Evan Siansuri ,  Reza Jalilizeinali ,  Michael Brunolli

    IPC: H02H9/04

    CPC classification number: H02H9/046 ,  G06F1/305 ,  H01L23/62 ,  H01L2924/0002 ,  H02H9/043 ,  H01L2924/00

    Abstract: In a particular embodiment, a circuit includes a power supply, a ground, and a clamping transistor circuit coupled to the power supply and to the ground. The circuit further includes a disable clamp circuit. The disable clamp circuit is coupled to the power supply and is responsive to a second power supply input to selectively disable the clamping transistor circuit by modifying a charging current applied to a capacitor of the clamping transistor circuit. In a particular embodiment, modifying the charging current includes enabling a second charging path. Enabling the second charging path enables charging the capacitor at a higher charging rate than a charging rate associated with charging the capacitor via a first charging path.

    Abstract translation: 在特定实施例中，电路包括耦合到电源和接地的电源，接地和钳位晶体管电路。 电路还包括禁止钳位电路。 禁止钳位电路耦合到电源，并且响应于第二电源输入，以通过修改施加到钳位晶体管电路的电容器的充电电流来选择性地禁止钳位晶体管电路。 在特定实施例中，修改充电电流包括实现第二充电路径。 启用第二充电路径使得能够以比通过第一充电路径对电容器充电相关的充电速率更高的充电速率对电容器进行充电。

Patent Agency Ranking