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    Static and intermittent dynamic multi-bias core for dual pad voltage level shifter
    1.
    发明授权
    Static and intermittent dynamic multi-bias core for dual pad voltage level shifter 有权

    公开(公告)号：US11171649B1

    公开(公告)日：2021-11-09

    申请号：US17071796

    申请日：2020-10-15

    Applicant: QUALCOMM Incorporated

    Inventor： Aliasgar Presswala ,  Wilson Jianbo Chen ,  Chiew-Guan Tan ,  Reza Jalilizeinali

    IPC: H03K19/003 ,  H03K19/0175 ,  H03K19/0185 ,  H03K3/356

    Abstract: An output driver in an integrated circuit includes a voltage shifter. The output driver has a low voltage section configured to provide a low voltage signal responsive to an input signal and a high voltage section configured to provide a high voltage signal responsive to the input signal. A first biasing circuit is configured to provide a bias to a first transistor in the high voltage section such that the bias is modified during a transition in the output signal. A second biasing circuit is configured to turn on a second transistor in the high voltage section when the output signal is at a low voltage level. The second transistor is configured to discharge a terminal of the first transistor. The input signal switches between 0 Volts and 0.9 Volts. The output signal switches between 0 Volts and 1.2 Volts or between 0 Volts and 1.8 Volts.

    Electrostatic protection for stacked multi-chip integrated circuits
    3.
    发明授权
    Electrostatic protection for stacked multi-chip integrated circuits 有权
    堆叠多芯片集成电路的静电保护

    公开(公告)号：US09184130B2

    公开(公告)日：2015-11-10

    申请号：US13646109

    申请日：2012-10-05

    Applicant: QUALCOMM Incorporated

    Inventor： Brian M. Henderson ,  Chiew-Guan Tan ,  Gregory A. Uvieghara ,  Reza Jalilizeinali

    IPC: H02H9/00 ,  H01L23/525 ,  H01L23/60 ,  H01L25/065 ,  H01L25/00 ,  H01L23/31 ,  H01L23/48

    CPC classification number: H01L23/5256 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/60 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/48091 ,  H01L2224/73257 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/00014

    Abstract: One feature pertains to a multi-chip module that comprises at least a first integrated circuit (IC) die and a second IC die. The second IC die has an input/output (I/O) node electrically coupled to the first IC die by a through substrate via. The second die's active surface also includes a fuse that is electrically coupled to the I/O node and adapted to protect the second IC die from damage caused by an electrostatic discharge (ESD). In particular, the fuse protects the second IC die from ESD that may be generated as a result of electrically coupling the first die to the second die during the manufacturing of the multi-chip module. Upon coupling the first die to the second die, the fuse may bypass the ESD current generated by the ESD to ground. After packaging of the multi-chip module is complete, the fuse may be blown open.

    Abstract translation: 一个特征涉及包括至少第一集成电路（IC）管芯和第二IC管芯的多芯片模块。 第二IC芯片具有通过基板通孔电耦合到第一IC裸片的输入/输出（I / O）节点。 第二管芯的有源表面还包括电连接到I / O节点并且适于保护第二IC管芯免受静电放电（ESD）引起的损坏的熔丝。 特别地，保险丝保护第二IC芯片免受由于在多芯片模块的制造期间将第一裸片电耦合到第二裸片而产生的ESD。 在将第一管芯耦合到第二管芯时，熔丝可以将由ESD产生的ESD电流旁路到地。 多芯片模块封装完成后，保险丝可能会断开。

    Systems and methods for wafer-level loopback test
    4.
    发明授权
    Systems and methods for wafer-level loopback test 有权

    公开(公告)号：US10114074B2

    公开(公告)日：2018-10-30

    申请号：US15955013

    申请日：2018-04-17

    Applicant: QUALCOMM Incorporated

    Inventor： Alvin Leng Sun Loke ,  Thomas Clark Bryan ,  Reza Jalilizeinali ,  Tin Tin Wee ,  Stephen Robert Knol ,  Luverne Ray Peterson

    IPC: G06F17/50 ,  G01R31/3177 ,  G01R31/3185 ,  G01R31/317

    Abstract: Circuits and methods for loopback testing are provided. A die incorporates a receiver (RX) to each transmitter (TX) as well as a TX to each RX. This architecture is applied to each bit so, e.g., a die that transmits or receives 32 data bits during operation would have 32 transceivers (one for each bit). Focusing on one of the transceivers, a loopback architecture includes a TX data path and an RX data path that are coupled to each other through an external contact, such as a via at the transceiver. The die further includes a transmit clock tree feeding the TX data path and a receive clock tree feeding the RX data path. The transmit clock tree feeds the receive clock tree through a conductive clock node that is exposed on a surface of the die. Some systems further include a variable delay in the clock path.

    Mixed mode RC clamps
    6.
    发明授权
    Mixed mode RC clamps 有权
    混合模式RC夹

    公开(公告)号：US09406627B2

    公开(公告)日：2016-08-02

    申请号：US14038663

    申请日：2013-09-26

    Applicant: QUALCOMM Incorporated

    Inventor： Eugene Robert Worley ,  Reza Jalilizeinali ,  Sreeker Dundigal

    IPC: H01L27/06 ,  H01L23/60 ,  H01L27/02 ,  H02H9/04

    CPC classification number: H01L23/60 ,  H01L27/0285 ,  H01L27/0682 ,  H01L2924/0002 ,  H02H9/046 ,  H01L2924/00

    Abstract: A system interconnect includes a first resistor-capacitor (RC) clamp having a first RC time constant. The system interconnect also includes second RC clamps having a second RC time constant. The first and second RC clamps are arranged along the system interconnect. In addition, the first RC time constant is different from the second RC time constant.

    Abstract translation: 系统互连包括具有第一RC时间常数的第一电阻器 - 电容（RC）钳位。 系统互连还包括具有第二RC时间常数的第二RC钳位。 第一和第二RC夹具沿着系统互连排列。 另外，第一RC时间常数与第二RC时间常数不同。

    ELECTROSTATIC DISCHARGE CIRCUIT WITH REDUCED STANDBY CURRENT
    7.
    发明申请
    ELECTROSTATIC DISCHARGE CIRCUIT WITH REDUCED STANDBY CURRENT 审中-公开
    具有降低待机电流的静电放电电路

    公开(公告)号：US20150249334A1

    公开(公告)日：2015-09-03

    申请号：US14194158

    申请日：2014-02-28

    Applicant: Qualcomm Incorporated

    Inventor： Wen-Yi Chen ,  Sreeker Dundigal ,  Reza Jalilizeinali ,  Eugene Robert Worley

    IPC: H02H9/04

    CPC classification number: H02H9/046

    Abstract: Techniques for reducing leakage current during normal operation of an electrostatic discharge (ESD) circuit are described herein. In one embodiment, a circuit comprises an internal circuit and an electrostatic discharge (ESD) rail clamp coupled in parallel to the internal circuit and between first and second power supply rails. The ESD rail clamp is operable to shunt ESD current from the first power supply rail to the second power supply rail via a low resistance shunt path. The ESD rail clamp comprises an ESD trigger circuit configured to detect an ESD event and a plurality of discharging transistors coupled in series. The ESD trigger circuit is configured to turn off the discharging transistors during normal operation and to turn on the discharging transistors to form the low resistance shunt path in response to detection of the ESD event.

    Abstract translation: 本文描述了用于在静电放电（ESD）电路的正常操作期间减小泄漏电流的技术。 在一个实施例中，电路包括与内部电路并联并且在第一和第二电源轨之间并联的内部电路和静电放电（ESD）导轨夹。 ESD导轨夹可用于通过低电阻分流路径将ESD电流从第一电源轨分流到第二电源轨。 ESD导轨夹具包括被配置为检测ESD事件的ESD触发电路和串联耦合的多个放电晶体管。 ESD触发电路被配置为在正常操作期间关闭放电晶体管，并且响应于ESD事件的检测而导通放电晶体管以形成低电阻分流路径。

    TRANSISTORS CONFIGURED FOR GATE OVERBIASING AND CIRCUITS THEREFROM
    9.
    发明申请
    TRANSISTORS CONFIGURED FOR GATE OVERBIASING AND CIRCUITS THEREFROM 有权
    晶闸管配置为栅极过渡和电路

    公开(公告)号：US20160269017A1

    公开(公告)日：2016-09-15

    申请号：US14812516

    申请日：2015-07-29

    Applicant: QUALCOMM Incorporated

    Inventor： Alvin Leng Sun Loke ,  Bo Yu ,  Stephen Clifford Thilenius ,  Reza Jalilizeinali ,  Patrick Isakanian

    IPC: H03K17/082

    CPC classification number: H03K17/0822 ,  H03K19/00315 ,  H03K19/018521

    Abstract: An electronic circuit and methods of operating the electronic circuit are provided. The electronic circuit includes a pull-up transistor for pulling up an input/output (I/O) node of the output circuit to a first voltage and a first isolation transistor for coupling the pull-up transistor to the I/O node. The electronic circuit also includes a pull-down transistor for pulling down the I/O node to a second voltage and a second isolation transistor for coupling the pull-down transistor to the I/O node. In the electronic circuit, the pull-up and the pull-down transistors are transistors supporting a first drain-to-source voltage and a first gate-to-source voltage, while the first and the second isolation transistors are transistors supporting the first drain-to-source voltage and a second gate-to-source voltage greater than the first gate-to-source voltage.

    Abstract translation: 提供电子电路和操作电子电路的方法。 电子电路包括用于将输出电路的输入/输出（I / O）节点提升到第一电压的上拉晶体管和用于将上拉晶体管耦合到I / O节点的第一隔离晶体管。 电子电路还包括用于将I / O节点下拉到第二电压的下拉晶体管和用于将下拉晶体管耦合到I / O节点的第二隔离晶体管。 在电子电路中，上拉和下拉晶体管是支持第一漏极 - 源极电压和第一栅极 - 源极电压的晶体管，而第一和第二隔离晶体管是支撑第一漏极 并且第二栅极至源极电压大于第一栅极至源极电压。

    OUTPUT DRIVER WITH BACK-POWERING PREVENTION
    10.
    发明申请
    OUTPUT DRIVER WITH BACK-POWERING PREVENTION 有权
    输出驱动器与备用电源预防

    公开(公告)号：US20160248418A1

    公开(公告)日：2016-08-25

    申请号：US14631347

    申请日：2015-02-25

    Applicant: QUALCOMM Incorporated

    Inventor： Wilson Jianbo Chen ,  Chiew-Guan Tan ,  Reza Jalilizeinali

    IPC: H03K17/26 ,  H03K17/18

    CPC classification number: H03K17/26 ,  H03K17/18 ,  H03K19/00315 ,  H03K19/00361

    Abstract: A back-power prevention circuit is provided that protects a buffer transistor from back-power during a back-power condition by charging a signal lead coupled to a gate of the buffer transistor to a pad voltage and by charging a body of the buffer transistor to the pad voltage.

    Abstract translation: 提供了一种后置功率防止电路，其通过将耦合到缓冲晶体管的栅极的信号引线充电到焊盘电压并且通过将缓冲晶体管的主体充电到基板来保护缓冲晶体管免受后功率状态下的反向功率 焊盘电压。

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