公开(公告)号：US10231324B2

公开(公告)日：2019-03-12

申请号：US14264836

申请日：2014-04-29

Applicant: QUALCOMM Incorporated

Inventor： Ryan David Lane ,  Yue Li ,  Charles David Paynter ,  Ruey Kae Zang

IPC: H01L21/48 ,  H05K1/02 ,  H01L21/768 ,  H01L23/498 ,  H01L23/528 ,  H01L23/522 ,  H01L23/525

Abstract: Some novel features pertain to an integrated device that includes a first metal layer and a second metal layer. The first metal layer includes a first set of regions. The first set of regions includes a first netlist structure for a power distribution network (PDN) of the integrated device. The second metal layer includes a second set of regions. The second set of regions includes a second netlist structure of the PDN of the integrated device. In some implementations, the second metal layer further includes a third set of regions comprising the first netlist structure for the PDN of the integrated device. In some implementations, the first metal layer includes a third set of regions that includes a third netlist structure for the PDN of the integrated device. The third set of regions is non-overlapping with the first set of regions of the first metal layer.

公开(公告)号：US20150228594A1

公开(公告)日：2015-08-13

申请号：US14221582

申请日：2014-03-21

Applicant: QUALCOMM INCORPORATED

Inventor： Reynante Tamunan Alvarado ,  Ruey Kae Zang ,  Lizabeth Ann Keser

IPC: H01L23/00 ,  H01L23/48

CPC classification number: H01L24/06 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/034 ,  H01L2224/0361 ,  H01L2224/03622 ,  H01L2224/05078 ,  H01L2224/05094 ,  H01L2224/05095 ,  H01L2224/05096 ,  H01L2224/05097 ,  H01L2224/051 ,  H01L2224/05548 ,  H01L2224/05559 ,  H01L2224/0556 ,  H01L2224/05562 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/061 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/01082 ,  H01L2924/00012

Abstract: A semiconductor device is provided that has a redistribution layer with reduced resistance. The semiconductor device comprises a plurality of bonding pads on a substrate, a redistribution layer coupled to the bonding pads through a plurality of vias, a dielectric layer over the redistribution layer, that includes an opening that exposes a portion of the redistribution layer. The bonding pads are at least partially under the opening.

Abstract translation: 提供了具有减小的电阻的再分布层的半导体器件。 半导体器件包括在衬底上的多个接合焊盘，通过多个通孔耦合到接合焊盘的再分布层，再分布层上的介电层，其包括暴露再分布层的一部分的开口。 接合垫至少部分在开口下方。

公开(公告)号：US10321575B2

公开(公告)日：2019-06-11

申请号：US14842403

申请日：2015-09-01

Applicant: QUALCOMM Incorporated

Inventor： Yue Li ,  Charles David Paynter ,  Ryan David Lane ,  Ruey Kae Zang

IPC: H05K1/18 ,  H01L21/56 ,  H01L23/498 ,  H05K1/03 ,  H05K1/11 ,  H01L23/64 ,  H01L21/48 ,  H01L23/13 ,  H01L23/16

Abstract: An integrated circuit (IC) module that includes an integrated circuit (IC) package, a plurality of first solder interconnects coupled to the IC package, an interposer coupled to the IC package through the plurality of first solder interconnects a plurality of second solder interconnects coupled to the interposer; and a printed circuit board (PCB) coupled to the interposer through the plurality of second solder interconnects. The interposer includes an encapsulation layer, a first passive component at least partially embedded in the encapsulation layer, and a plurality of interconnects coupled to the first passive component. The encapsulation layer includes a mold and/or an epoxy fill. The first passive component is configured to operate as an electronic voltage regulator (EVR) for the IC module. In some implementations, the interposer is a fan out interposer.

公开(公告)号：US09041176B2

公开(公告)日：2015-05-26

申请号：US13764356

申请日：2013-02-11

Applicant: Qualcomm Incorporated

Inventor： Yue Li ,  Charles D. Paynter ,  Ruey Kae Zang

IPC: H01L23/02 ,  H01L21/00 ,  H01L21/82 ,  H01L49/02 ,  H01L25/065

CPC classification number: H01L21/82 ,  H01L25/065 ,  H01L25/0657 ,  H01L28/00 ,  H01L2224/16225 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/19105 ,  Y10T29/53174

Abstract: Some implementations provide a structure that includes a first package substrate, a first component, a second package substrate, a second component, and a third component. The first package substrate has a first area. The first component has a first height and is positioned on the first area. The second package substrate is coupled to the first package substrate. The second package substrate has second and third areas. The second area of the second package substrate vertically overlaps with the first area of the first package substrate The third area of the second package substrate is non-overlapping with the first area of the first package substrate. The second component has a second height and is positioned on the second area. The third component is positioned on the third area. The third component has a third height that is greater than each of the first and second heights.

Abstract translation: 一些实施方案提供了包括第一封装衬底，第一部件，第二封装衬底，第二部件和第三部件的结构。 第一封装衬底具有第一区域。 第一部件具有第一高度并且位于第一区域上。 第二封装衬底耦合到第一封装衬底。 第二封装衬底具有第二和第三区域。 第二封装衬底的第二区域垂直地与第一封装衬底的第一区域重叠。第二封装衬底的第三区域与第一封装衬底的第一区域不重叠。 第二部件具有第二高度并且位于第二区域上。 第三个组件位于第三个区域。 第三部件具有大于第一和第二高度中的每一个的第三高度。

公开(公告)号：US20140097512A1

公开(公告)日：2014-04-10

申请号：US13764356

申请日：2013-02-11

Applicant: QUALCOMM INCORPORATED

Inventor： Yue Li ,  Charles D. Paynter ,  Ruey Kae Zang

IPC: H01L21/82

CPC classification number: H01L21/82 ,  H01L25/065 ,  H01L25/0657 ,  H01L28/00 ,  H01L2224/16225 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/19105 ,  Y10T29/53174

Abstract: Some implementations provide a structure that includes a first package substrate, a first component, a second package substrate, a second component, and a third component. The first package substrate has a first area. The first component has a first height and is positioned on the first area. The second package substrate is coupled to the first package substrate. The second package substrate has second and third areas. The second area of the second package substrate vertically overlaps with the first area of the first package substrate The third area of the second package substrate is non-overlapping with the first area of the first package substrate. The second component has a second height and is positioned on the second area. The third component is positioned on the third area. The third component has a third height that is greater than each of the first and second heights.

Abstract translation: 一些实施方案提供了包括第一封装衬底，第一部件，第二封装衬底，第二部件和第三部件的结构。 第一封装衬底具有第一区域。 第一部件具有第一高度并且位于第一区域上。 第二封装衬底耦合到第一封装衬底。 第二封装衬底具有第二和第三区域。 第二封装衬底的第二区域垂直地与第一封装衬底的第一区域重叠。第二封装衬底的第三区域与第一封装衬底的第一区域不重叠。 第二部件具有第二高度并且位于第二区域上。 第三个组件位于第三个区域。 第三部件具有大于第一和第二高度中的每一个的第三高度。

公开(公告)号：US20170064837A1

公开(公告)日：2017-03-02

申请号：US14842403

申请日：2015-09-01

Applicant: QUALCOMM Incorporated

Inventor： Yue Li ,  Charles David Paynter ,  Ryan David Lane ,  Ruey Kae Zang

IPC: H05K1/18 ,  H01L21/56 ,  H01L23/498 ,  H05K1/03 ,  H05K1/11

CPC classification number: H05K1/186 ,  H01L21/4857 ,  H01L21/50 ,  H01L21/56 ,  H01L23/13 ,  H01L23/16 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/64 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19106 ,  H05K1/0306 ,  H05K1/0313 ,  H05K1/113 ,  H05K1/114 ,  H05K2201/10015 ,  H05K2201/1003 ,  H01L2924/014 ,  H01L2924/00014

Abstract: An integrated circuit (IC) module that includes an integrated circuit (IC) package, a plurality of first solder interconnects coupled to the IC package, an interposer coupled to the IC package through the plurality of first solder interconnects a plurality of second solder interconnects coupled to the interposer; and a printed circuit board (PCB) coupled to the interposer through the plurality of second solder interconnects. The interposer includes an encapsulation layer, a first passive component at least partially embedded in the encapsulation layer, and a plurality of interconnects coupled to the first passive component. The encapsulation layer includes a mold and/or an epoxy fill. The first passive component is configured to operate as an electronic voltage regulator (EVR) for the IC module. In some implementations, the interposer is a fan out interposer.

Abstract translation: 一种集成电路（IC）模块，其包括集成电路（IC）封装，耦合到所述IC封装的多个第一焊料互连件，通过所述多个第一焊料互连而耦合到所述IC封装的插入件，多个第二焊料互连 到中介者 以及通过所述多个第二焊料互连件耦合到所述插入件的印刷电路板（PCB）。 插入器包括封装层，至少部分地嵌入封装层中的第一无源元件以及耦合到第一无源元件的多个互连。 封装层包括模具和/或环氧树脂填充物。 第一个无源组件配置为作为IC模块的电子稳压器（EVR）运行。 在一些实现中，插入器是扇出插件。

公开(公告)号：US20150313006A1

公开(公告)日：2015-10-29

申请号：US14264836

申请日：2014-04-29

Applicant: QUALCOMM Incorporated

Inventor： Ryan David Lane ,  Yue Li ,  Charles David Paynter ,  Ruey Kae Zang

IPC: H05K1/02 ,  H01L21/48 ,  H05K3/00 ,  H01L23/528 ,  H01L23/498 ,  H01L21/768 ,  H01L23/522

CPC classification number: H05K1/0216 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/525 ,  H01L23/5286 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K1/0225 ,  H05K1/0236 ,  H05K2201/09309

Abstract: Some novel features pertain to an integrated device that includes a first metal layer and a second metal layer. The first metal layer includes a first set of regions. The first set of regions includes a first netlist structure for a power distribution network (PDN) of the integrated device. The second metal layer includes a second set of regions. The second set of regions includes a second netlist structure of the PDN of the integrated device. In some implementations, the second metal layer further includes a third set of regions comprising the first netlist structure for the PDN of the integrated device. In some implementations, the first metal layer includes a third set of regions that includes a third netlist structure for the PDN of the integrated device. The third set of regions is non-overlapping with the first set of regions of the first metal layer.

Abstract translation: 一些新颖的特征涉及包括第一金属层和第二金属层的集成器件。 第一金属层包括第一组区域。 第一组区域包括用于集成设备的配电网络（PDN）的第一网表结构。 第二金属层包括第二组区域。 第二组区域包括集成设备的PDN的第二网表结构。 在一些实现中，第二金属层还包括第三组区域，其包括用于集成设备的PDN的第一网表结构。 在一些实现中，第一金属层包括第三组区域，其包括用于集成设备的PDN的第三网表结构。 第三组区域与第一金属层的第一组区域不重叠。