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    Phase-locked loop (PLL) with charge scaling
    2.
    发明授权
    Phase-locked loop (PLL) with charge scaling 有权

    公开(公告)号：US10135448B1

    公开(公告)日：2018-11-20

    申请号：US15710751

    申请日：2017-09-20

    Applicant: Qualcomm Incorporated

    Inventor： Alireza Khalili ,  Amir Ziabasharhagh

    IPC: H03L7/06 ,  H03L7/08 ,  H03L7/089 ,  H03L7/093

    Abstract: An integrated circuit is disclosed that implements a phase-locked loop with charge scaling. In an example aspect, the integrated circuit includes a charge pump, a filter, and a charge manager. The charge pump generates a current signal, and the filter includes a filter capacitor. The charge manager is coupled between the charge pump and the filter. The charge manager includes current-sampling capacitance circuitry and a charge manager controller that is coupled to the current-sampling capacitance circuitry. The current-sampling capacitance circuitry receives the current signal from the charge pump and retains charge from the current signal to create stored charge, with the stored charge including a first charge portion and a second charge portion. The charge manager controller causes the current-sampling capacitance circuitry to communicate the first charge portion to the filter capacitor and causes the current-sampling capacitance circuitry to divert the second charge portion away from the filter capacitor.

    LOW-POWER BALANCED CRYSTAL OSCILLATOR
    3.
    发明申请
    LOW-POWER BALANCED CRYSTAL OSCILLATOR 有权
    低功耗平衡振荡器

    公开(公告)号：US20160380590A1

    公开(公告)日：2016-12-29

    申请号：US14748946

    申请日：2015-06-24

    Applicant: QUALCOMM Incorporated

    Inventor： Alireza Khalili ,  Yashar Rajavi ,  Mazhareddin Taghivand

    IPC: H03B5/36

    CPC classification number: H03B5/364 ,  H03B5/1212 ,  H03B5/1228 ,  H03B2200/0036 ,  H03B2200/0082

    Abstract: A circuit includes: first and second output terminals; a reference resonator coupled between the first and second output terminals; a cross-coupled oscillation unit coupled to the first and second output terminals; a first MOSFET diode coupled to the cross-coupled oscillation unit, the first MOSFET diode including a first transistor, a first resistor coupled between gate and drain terminals of the first transistor, and a first capacitor; a second MOSFET diode coupled to the cross-coupled oscillation unit, the second MOSFET diode including a second transistor, a second resistor coupled between gate and drain terminals of the second transistor, and a second capacitor cross coupled between the drain terminal of the second transistor and the gate terminal of the first transistor, wherein the first capacitor is cross coupled between the drain terminal of the first transistor and the gate terminal of the second transistor.

    Abstract translation: 电路包括：第一和第二输出端子; 耦合在所述第一和第二输出端子之间的参考谐振器; 耦合到所述第一和第二输出端子的交叉耦合振荡单元; 耦合到所述交叉耦合振荡单元的第一MOSFET二极管，所述第一MOSFET二极管包括第一晶体管，耦合在所述第一晶体管的栅极和漏极端子之间的第一电阻器和第一电容器; 耦合到交叉耦合振荡单元的第二MOSFET二极管，所述第二MOSFET二极管包括第二晶体管，耦合在所述第二晶体管的栅极和漏极端子之间的第二电阻器以及耦合在所述第二晶体管的漏极端子之间的第二电容器 和第一晶体管的栅极端子，其中第一电容器交叉耦合在第一晶体管的漏极端子和第二晶体管的栅极端子之间。

    Apparatus and method for generating quadrupled reference clock from single ended crystal oscillator
    4.
    发明授权
    Apparatus and method for generating quadrupled reference clock from single ended crystal oscillator 有权
    从单端晶体振荡器产生四倍参考时钟的装置和方法

    公开(公告)号：US09490784B2

    公开(公告)日：2016-11-08

    申请号：US14640672

    申请日：2015-03-06

    Applicant: QUALCOMM Incorporated

    Inventor： Mohammad Bagher Vahid Far ,  Alireza Khalili ,  Yashar Rajavi ,  Amirpouya Kavousian

    IPC: H03B19/14 ,  H03K5/156 ,  H03K5/00 ,  H03B19/10

    CPC classification number: H03K5/00006 ,  H03B19/10 ,  H03B19/14 ,  H03K5/1565

    Abstract: A method, an apparatus, and a computer program product are provided. The apparatus outputs a sinusoidal signal according to a first clock frequency, generates, a first digital signal having a 25% duty cycle based on the sinusoidal signal, generates a second digital signal having a 25% duty cycle based on the sinusoidal signal, combines the first digital signal and the second digital signal to generate a combined digital signal having a 50% duty cycle and a second clock frequency that is double the first clock frequency, and doubles the second clock frequency of the combined digital signal to generate an output signal having a third clock frequency that is quadruple the first clock frequency. The apparatus further generates a first control voltage and a second control voltage for the first buffer and a third control voltage for the second buffer based on the output signal.

    Abstract translation: 提供了一种方法，装置和计算机程序产品。 该装置根据第一时钟频率输出正弦信号，产生基于正弦信号的具有25％占空比的第一数字信号，产生基于正弦信号具有25％占空比的第二数字信号， 第一数字信号和第二数字信号，以产生具有50％占空比和第二时钟频率的组合数字信号，该第二时钟频率是第一时钟频率的两倍，并且使组合数字信号的第二时钟频率加倍，以产生具有 第三个时钟频率是第一个时钟频率的四倍。 该装置还基于输出信号产生用于第一缓冲器的第一控制电压和第二控制电压以及第二缓冲器的第三控制电压。

    Increased synthesizer performance in carrier aggregation/multiple-input, multiple-output systems
    5.
    发明授权
    Increased synthesizer performance in carrier aggregation/multiple-input, multiple-output systems 有权
    在载波聚合/多输入多输出系统中增加合成器性能

    公开(公告)号：US09444473B2

    公开(公告)日：2016-09-13

    申请号：US14548705

    申请日：2014-11-20

    Applicant: QUALCOMM Incorporated

    Inventor： Alireza Khalili ,  Mazhareddin Taghivand ,  Arvind Keerti

    IPC: H03L7/099 ,  H03B5/12 ,  H04B1/00

    CPC classification number: H03L7/099 ,  H03B5/1212 ,  H04B1/005 ,  H04B1/0064

    Abstract: Certain aspects of the present disclosure provide methods and apparatus for using multiple voltage-controlled oscillators (VCOs) to increase frequency synthesizer performance, such as in stringent multiple-input, multiple-output (MIMO) modes. One example apparatus capable of generating oscillating signals generally includes a first VCO, a second VCO, and connection circuitry configured to connect the second VCO in parallel with the first VCO if a phase-locked loop (PLL) associated with the second VCO is idle.

    Abstract translation: 本公开的某些方面提供了使用多个压控振荡器（VCO）来增加频率合成器性能的方法和装置，例如在严格的多输入多输出（MIMO）模式中。 能够产生振荡信号的一个示例性装置通常包括第一VCO，第二VCO和连接电路，其被配置为如果与第二VCO相关联的锁相环（PLL）空闲，则将第二VCO与第一VCO并联连接。

    ADAPTIVE ANALOG INTERFERENCE CANCELLING SYSTEM AND METHOD FOR RF RECEIVERS
    6.
    发明申请
    ADAPTIVE ANALOG INTERFERENCE CANCELLING SYSTEM AND METHOD FOR RF RECEIVERS 审中-公开

    公开(公告)号：US20180131397A1

    公开(公告)日：2018-05-10

    申请号：US15343791

    申请日：2016-11-04

    Applicant: QUALCOMM Incorporated

    Inventor： Mohammad Emadi ,  Mazhareddin Taghivand ,  Alireza Khalili

    IPC: H04B1/10 ,  H04L27/14

    CPC classification number: H04B1/1081 ,  H04B1/1036 ,  H04B1/525 ,  H04L27/14

    Abstract: A method of and system for processing a received signal is disclosed. The method includes generating a corrected radio frequency (RF) signal based on an RF feedback signal and an incoming RF signal, the incoming RF signal includes a wanted signal and an interfering signal. The method also includes down-converting the corrected RF signal to a corrected in-phase baseband signal and a corrected quadrature-phase baseband signal; extracting, based on a baseband signal of an aggressor signal, an in-phase baseband signal of the interfering signal from the corrected in-phase baseband signal; extracting, based on the baseband signal of the aggressor, a quadrature-phase baseband signal of the interfering signal from the corrected quadrature-phase baseband signal; up-converting the extracted interfering signals to produce the RF feedback signal; and generating a second corrected RF signal based on the second RF feedback signal and the incoming RF signal.

    Leakage compensation circuit for phase-locked loop (PLL) large thin oxide capacitors
    8.
    发明授权
    Leakage compensation circuit for phase-locked loop (PLL) large thin oxide capacitors 有权
    漏电补偿电路用于锁相环（PLL）大型薄氧化物电容器

    公开(公告)号：US09455723B2

    公开(公告)日：2016-09-27

    申请号：US14743360

    申请日：2015-06-18

    Applicant: QUALCOMM Incorporated

    Inventor： Mohammad Bagher Vahid Far ,  Ara Bicakci ,  Alireza Khalili ,  Ashkan Borna ,  Thinh Cat Nguyen

    IPC: H03L7/06 ,  H03L7/08 ,  H03L7/093 ,  H02M3/07

    CPC classification number: H03L7/0802 ,  H02M3/07 ,  H03L7/0891 ,  H03L7/093

    Abstract: Certain aspects of the present disclosure provide methods and apparatus for compensating, or at least adjusting, for capacitor leakage. One example method generally includes determining a leakage voltage corresponding to a leakage current of a capacitor in a filter for a phase-locked loop (PLL), wherein the determining comprises closing a set of switches for discontinuous sampling of the leakage voltage; based on the sampled leakage voltage, generating a sourced current approximately equal to the leakage current; and injecting the sourced current into the capacitor.

    Abstract translation: 本公开的某些方面提供了用于补偿或至少调整电容器泄漏的方法和装置。 一个示例性方法通常包括确定对应于用于锁相环（PLL）的滤波器中的电容器的漏电流的泄漏电压，其中所述确定包括闭合一组开关以不连续地采样泄漏电压; 基于采样的泄漏电压，产生大致等于泄漏电流的源电流; 并将源电流注入电容器。

    Differential crystal oscillator circuit
    9.
    发明授权
    Differential crystal oscillator circuit 有权
    差分晶振电路

    公开(公告)号：US09300249B2

    公开(公告)日：2016-03-29

    申请号：US14338241

    申请日：2014-07-22

    Applicant: QUALCOMM Incorporated

    Inventor： Yashar Rajavi ,  Amirpouya Kavousian ,  Alireza Khalili ,  Mohammad Bagher Vahid Far ,  Abbas Komijani

    IPC: H03B5/32 ,  H03B5/36

    CPC classification number: H03B5/364 ,  H03B5/06 ,  H03B5/36 ,  H03B2200/004 ,  H03B2200/0094

    Abstract: A differential crystal oscillator circuit, including: first and second output terminals; a cross-coupled oscillation unit including first and second transistors cross-coupled to the first and second output terminals; first and second metal-oxide semiconductor field-effect transistor (MOSFET) diodes, each MOSFET diode including a resistor connected between gate and drain terminals, wherein the first MOSFET diode couples to the first transistor to provide low-impedance load at low frequencies and high-impedance load at higher frequencies to the first transistor, wherein the second MOSFET diode couples to the second transistor to provide low-impedance load at low frequencies and high-impedance load at higher frequencies to the second transistor; and a reference resonator coupled between the first and second output terminals to establish an oscillation frequency.

    Abstract translation: 一种差分晶体振荡器电路，包括：第一和第二输出端子; 交叉耦合振荡单元，包括交叉耦合到第一和第二输出端的第一和第二晶体管; 第一和第二金属氧化物半导体场效应晶体管（MOSFET）二极管，每个MOSFET二极管包括连接在栅极和漏极端子之间的电阻器，其中第一MOSFET二极管耦合到第一晶体管以在低频和高电平下提供低阻抗负载 在第一晶体管的较高频率处的阻抗负载，其中所述第二MOSFET二极管耦合到所述第二晶体管，以在低频处提供低阻抗负载，并以较高频率向所述第二晶体管提供高阻抗负载; 以及耦合在第一和第二输出端子之间以建立振荡频率的参考谐振器。

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