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    Quadrature frequency doubler with adjustable phase offset
    4.
    发明授权
    Quadrature frequency doubler with adjustable phase offset 有权
    具有可调相位偏移的正交倍频器

    公开(公告)号：US07978785B2

    公开(公告)日：2011-07-12

    申请号：US11677400

    申请日：2007-02-21

    申请人： Curtis Leifso

    发明人： Curtis Leifso

    IPC分类号： H03B19/00

    CPC分类号： H03B19/14 ,  H03B2200/0036 ,  H03B2200/0078

    摘要： The present invention provides an improved frequency doubling circuit, with adjustable phase offset. Briefly, rather than using the traditional equations cos (2ωt)=cos 2(ωt)−sin 2(ωt) and sin(2ωt)=2 sin(ωt)cos(ωt), the quadrature output signals are generated utilizing mixers, each having two input signals, separated in phase by the same offset. This minimizes the effects of the non-linearities introduced by the mixer, which therefore reduces amplitude mismatch between the quadrature signals. Also, the phase offset of the quadrature output signals can be tuned and calibrated using a phase shifting circuit. This phase shifting circuit realizes a tuning range of approximately 5° in programmable steps. This combination of circuits can be used to minimize the amplitude mismatch and phase errors, thereby reducing the amplitude of and interference caused by transmission of the image frequency to the receivers input.

    摘要翻译： 本发明提供了具有可调相位偏移的改进的倍频电路。 简而言之，不是使用传统方程cos（2ωt）= cos 2（ωt）-sin 2（ωt）和sin（2ωt）= 2sin（ωt）cos（ωt），正交输出信号是利用混频器产生的， 具有两个输入信号，其相位偏移相同。 这使得由混频器引入的非线性的影响最小化，因此减小正交信号之间的幅度失配。 此外，正交输出信号的相位偏移可以使用移相电路进行调谐和校准。 该相移电路在可编程步骤中实现大约5°的调谐范围。 电路的这种组合可用于最小化幅度失配和相位误差，从而减少由图像频率传输到接收器输入引起的幅度和干扰。

    Radio frequency doubler
    5.
    发明申请
    Radio frequency doubler 失效

    公开(公告)号：US20080054955A1

    公开(公告)日：2008-03-06

    申请号：US11819232

    申请日：2007-06-26

    申请人： Junji Ito

    发明人： Junji Ito

    IPC分类号： H03B19/00

    CPC分类号： H03B19/14 ,  H03B2200/0036 ,  H03B2200/0098 ,  H03D7/1433 ,  H03D7/1441 ,  H03D7/1458 ,  H03D2200/0025 ,  H03D2200/0047

    摘要： When a signal of a double frequency is generated from the original signal, conventionally a 90-degree phase-shift circuit is necessary to suppress an output of a DC component and efficiently obtain a double wave. According to the present invention, an equal RF signal is inputted to input terminals and an output is matched with a frequency as high as that of the original frequency in a Gillbert cell double-balanced mixer, so that a doubled output is obtained with no DC offset. According to the circuit configuration of the present invention, it is possible to provide a circuit readily performing integration and to efficiently output only a double frequency merely by inputting a simple differential signal without the need for the original signal which has been phase controlled. Further, a DC short circuit in the resonance circuit makes it possible to eliminate a DC offset voltage in an output.

    LOW-POWER BALANCED CRYSTAL OSCILLATOR
    7.
    发明申请
    LOW-POWER BALANCED CRYSTAL OSCILLATOR 有权
    低功耗平衡振荡器

    公开(公告)号：US20160380590A1

    公开(公告)日：2016-12-29

    申请号：US14748946

    申请日：2015-06-24

    申请人： QUALCOMM Incorporated

    发明人： Alireza Khalili ,  Yashar Rajavi ,  Mazhareddin Taghivand

    IPC分类号： H03B5/36

    CPC分类号： H03B5/364 ,  H03B5/1212 ,  H03B5/1228 ,  H03B2200/0036 ,  H03B2200/0082

    摘要： A circuit includes: first and second output terminals; a reference resonator coupled between the first and second output terminals; a cross-coupled oscillation unit coupled to the first and second output terminals; a first MOSFET diode coupled to the cross-coupled oscillation unit, the first MOSFET diode including a first transistor, a first resistor coupled between gate and drain terminals of the first transistor, and a first capacitor; a second MOSFET diode coupled to the cross-coupled oscillation unit, the second MOSFET diode including a second transistor, a second resistor coupled between gate and drain terminals of the second transistor, and a second capacitor cross coupled between the drain terminal of the second transistor and the gate terminal of the first transistor, wherein the first capacitor is cross coupled between the drain terminal of the first transistor and the gate terminal of the second transistor.

    摘要翻译： 电路包括：第一和第二输出端子; 耦合在所述第一和第二输出端子之间的参考谐振器; 耦合到所述第一和第二输出端子的交叉耦合振荡单元; 耦合到所述交叉耦合振荡单元的第一MOSFET二极管，所述第一MOSFET二极管包括第一晶体管，耦合在所述第一晶体管的栅极和漏极端子之间的第一电阻器和第一电容器; 耦合到交叉耦合振荡单元的第二MOSFET二极管，所述第二MOSFET二极管包括第二晶体管，耦合在所述第二晶体管的栅极和漏极端子之间的第二电阻器以及耦合在所述第二晶体管的漏极端子之间的第二电容器 和第一晶体管的栅极端子，其中第一电容器交叉耦合在第一晶体管的漏极端子和第二晶体管的栅极端子之间。

    Radio frequency doubler
    9.
    发明授权
    Radio frequency doubler 有权
    射频倍频器

    公开(公告)号：US07245164B2

    公开(公告)日：2007-07-17

    申请号：US11058225

    申请日：2005-02-16

    申请人： Junji Ito

    发明人： Junji Ito

    IPC分类号： H03B19/00

    CPC分类号： H03B19/14 ,  H03B2200/0036 ,  H03B2200/0098 ,  H03D7/1433 ,  H03D7/1441 ,  H03D7/1458 ,  H03D2200/0025 ,  H03D2200/0047

    摘要： When a signal of a double frequency is generated from the original signal, conventionally a 90-degree phase-shift circuit is necessary to suppress an output of a DC component and efficiently obtain a double wave. According to the present invention, an equal RF signal is inputted to input terminals and an output is matched with a frequency as high as that of the original frequency in a Gillbert cell double-balanced mixer, so that a doubled output is obtained with no DC offset. According to the circuit configuration of the present invention, it is possible to provide a circuit readily performing integration and to efficiently output only a double frequency merely by inputting a simple differential signal without the need for the original signal which has been phase controlled. Further, a DC short circuit in the resonance circuit makes it possible to eliminate a DC offset voltage in an output.

    摘要翻译： 当从原始信号产生双倍频率的信号时，通常需要90度相移电路来抑制DC分量的输出并有效地获得双波。 根据本发明，将相同的RF信号输入到输入端子，并且在吉尔伯特单元双平衡混频器中将输出与原始频率的频率相匹配，从而获得没有DC的双倍输出 抵消。 根据本发明的电路结构，可以提供容易进行集成的电路，并且仅通过输入简单的差分信号即可有效地输出双倍频率，而不需要相位控制的原始信号。 此外，谐振电路中的DC短路使得可以消除输出中的DC偏移电压。

    Device of the phase-locked loop type for demodulating a frequency-modulated signal
    10.
    发明授权
    Device of the phase-locked loop type for demodulating a frequency-modulated signal 失效
    用于解调频率调制信号的锁相环类型的装置

    公开(公告)号：US5786726A

    公开(公告)日：1998-07-28

    申请号：US741166

    申请日：1996-10-29

    申请人： Pascal Lemasson

    发明人： Pascal Lemasson

    IPC分类号： H04N5/455 ,  H03B1/00 ,  H03B5/12 ,  H03D3/02 ,  H03D3/24 ,  H03L7/099 ,  H03D3/00 ,  H03B5/08 ,  H03H11/48

    CPC分类号： H03D3/241 ,  H03B5/1209 ,  H03B5/1231 ,  H03B5/1243 ,  H03B2200/0036 ,  H03B2200/0092 ,  H03B2201/02 ,  H03D2200/0019

    摘要： Device of the phase-locked loop type for demodulating a frequency-modulated signal. Device for frequency demodulation, using a phase-locked loop. According to the invention, for linearizing the variation of the frequency of a local oscillator (11) as a function of its control signal (Vb), a variable capacitance (Cv) is formed by an electronic module (20) which supplies the equivalent of a capacitance whose variation as a function of the control voltage (Vb) has a linearity deviation which is established for compensating the linearity deviation of the frequency of the oscillator as a function of the value of the capacitance (Cv).

    摘要翻译： 用于解调频率调制信号的锁相环类型的装置。 用于频率解调的装置，使用锁相环。 根据本发明，为了将本地振荡器（11）的频率变化作为其控制信号（Vb）的函数进行线性化，可变电容（Cv）由电子模块（20）形成，电子模块（20）提供相当于 作为控制电压（Vb）的函数的变化的电容具有作为用于补偿作为电容值（Cv）的函数的振荡器的频率的线性偏差而建立的线性偏差。