公开(公告)号：US09966962B2

公开(公告)日：2018-05-08

申请号：US15044024

申请日：2016-02-15

申请人： Panasonic Corporation

发明人： Takayuki Abe ,  Junji Sato

IPC分类号： H03L7/00 ,  H03L7/099 ,  H03B5/12 ,  H03K3/027 ,  H03B5/24 ,  H03K5/003

CPC分类号： H03L7/00 ,  H03B5/1209 ,  H03B5/1212 ,  H03B5/1228 ,  H03B5/1278 ,  H03B5/24 ,  H03B2200/0088 ,  H03K3/027 ,  H03K5/003 ,  H03L7/099

摘要： An oscillation signal generation circuit includes an oscillator and a calibration circuit. The oscillator includes a reference signal source circuit that has a reference signal source outputting a reference signal and converts the output reference signal into a control voltage, a filter that includes a variable resistance and a capacitance and removes noise in the control voltage, a transistor that converts the control voltage which has passed through the filter into a control current and outputs the control current, a core circuit that is driven by the control current and generates an output signal, and an output terminal that outputs the generated output signal. The calibration circuit is connected to the output terminal of the oscillator, detects whether or not the generated output signal is oscillating, and adjusts the current value of the control current by controlling the resistance value of the variable resistance in accordance with the detection result.

公开(公告)号：US09444400B2

公开(公告)日：2016-09-13

申请号：US14666084

申请日：2015-03-23

申请人： QUALCOMM Incorporated

发明人： Mazhareddin Taghivand ,  Keplin Victor Johansen

IPC分类号： H03B5/12

CPC分类号： H03B5/1262 ,  H03B5/1203 ,  H03B5/1206 ,  H03B5/1209 ,  H03B5/1228 ,  H03B5/1243 ,  H03B5/1265 ,  H03B5/129

摘要： Systems and methods for biasing frequency oscillators to minimize phase noise are disclosed. The system may comprise a tank circuit having an inductor, at least a first coupling capacitor and a second coupling capacitor. The system may further comprise a varactor circuit electrically connected to the first coupling capacitor and the second coupling capacitor. The system may further comprise at least one first metal oxide semiconductor (MOS) device electrically connected in shunt with the tank circuit and a bias voltage. The at least one first MOS device may be electrically connected to a first gate bias voltage configured to bias the at least one first MOS device such that a first gate-to-source voltage of the at least one first MOS device remains below the first threshold voltage.

摘要翻译： 公开了用于偏置频率振荡器以最小化相位噪声的系统和方法。 该系统可以包括具有电感器，至少第一耦合电容器和第二耦合电容器的振荡电路。 该系统还可以包括电连接到第一耦合电容器和第二耦合电容器的变容二极管电路。 该系统可以进一步包括至少一个第一金属氧化物半导体（MOS）器件，其电连接到与谐振电路并联的偏置电压。 至少一个第一MOS器件可以电连接到第一栅极偏置电压，其被配置为偏置至少一个第一MOS器件，使得至少一个第一MOS器件的第一栅极至源极电压保持低于第一阈值 电压。

公开(公告)号：US07772929B2

公开(公告)日：2010-08-10

申请号：US10541049

申请日：2004-01-27

申请人： Nicola Da Dalt

发明人： Nicola Da Dalt

IPC分类号： H03L7/099

CPC分类号： H03K3/354 ,  H03B5/1209 ,  H03B5/1215 ,  H03B5/1221 ,  H03B5/1228 ,  H03B5/1253 ,  H03B5/1265 ,  H03B5/1271 ,  H03B2200/0048 ,  H03B2200/005 ,  H03J2200/10 ,  H03K3/0322

摘要： A method and a device are proposed for frequency synthesis by means of oscillator means, particularly a digitally controlled oscillator, which are capable of generating output frequencies out of a set of possible output frequencies. For the purpose of generating a desired frequency that is not included in the set of possible output frequencies, the oscillator means are driven by a control device in such a way that said oscillator means alternately generate at least two different output frequencies, out of the set of possible output frequencies, in such a way that the average value of the generated output frequencies over a time period is substantially the desired frequency.

摘要翻译： 提出了一种通过振荡器装置，特别是数字控制振荡器进行频率合成的方法和装置，其能够产生一组可能的输出频率的输出频率。 为了产生不包括在可能的输出频率的集合中的期望频率，振荡器装置由控制装置驱动，使得所述振荡器装置交替地产生至少两个不同的输出频率 可能的输出频率，使得在一段时间内所产生的输出频率的平均值基本上是期望的频率。

公开(公告)号：US07724102B2

公开(公告)日：2010-05-25

申请号：US11861292

申请日：2007-09-26

申请人： Igor Ullmann

发明人： Igor Ullmann

IPC分类号： H03B5/12

CPC分类号： H03B5/1228 ,  H03B5/1209 ,  H03B5/1253 ,  H03B5/1296 ,  H03B2201/0208

摘要： An apparatus described herein is an LC tank circuit that may include a capacitance, a first inductance, and a second inductance. The first inductance and the second inductance may each be center tapped coils.

摘要翻译： 这里描述的装置是可以包括电容，第一电感和第二电感的LC槽电路。 第一电感和第二电感可以各自为中心抽头线圈。

公开(公告)号：US07449964B2

公开(公告)日：2008-11-11

申请号：US11120738

申请日：2005-05-03

申请人： Guangming Yin ,  Bo Zhang ,  Ichiro Fujimori

发明人： Guangming Yin ,  Bo Zhang ,  Ichiro Fujimori

IPC分类号： H03L7/00

CPC分类号： H03L7/10 ,  H03B5/1209 ,  H03B5/1212 ,  H03B5/1228 ,  H03B5/124 ,  H03B5/1265 ,  H03L7/099 ,  H04J3/04 ,  H04J3/0629 ,  H04L7/0008

摘要： The present invention provides a method for tuning output drivers to an operating frequency based on settings used to tune other devices within the device such as a VCO. First the VCO within a PLL and clock circuit is tuned to the desired operating frequency. This operating frequency then corresponds to a discrete tuning setting. The discrete setting that causes the VCO to function at the operating frequency are then transferred to scaled amplifiers within output drivers. These drivers are then tuned to the operating frequency with these settings. This process eliminates the need to individually tune each output driver to function properly at the operating frequency.

摘要翻译： 本发明提供了一种用于基于用于调谐诸如VCO的设备内的其它设备的设置来将输出驱动器调谐到工作频率的方法。 首先将PLL和时钟电路中的VCO调谐到所需的工作频率。 此工作频率对应于离散调谐设置。 导致VCO在工作频率下工作的离散设置随后被传送到输出驱动器内的缩放放大器。 然后通过这些设置将这些驱动程序调整到工作频率。 该过程无需单独调整每个输出驱动器在工作频率下正常工作。

公开(公告)号：US20080036536A1

公开(公告)日：2008-02-14

申请号：US11889939

申请日：2007-08-17

申请人： Haideh Khorramabadi

发明人： Haideh Khorramabadi

IPC分类号： H03F3/45 ,  H03F3/18

CPC分类号： H03F1/3211 ,  H01F17/0013 ,  H01F2017/0053 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/3011 ,  H03B5/1209 ,  H03B5/1212 ,  H03B5/1228 ,  H03F1/52 ,  H03F1/523 ,  H03F3/191 ,  H03F3/195 ,  H03F3/24 ,  H03F3/45188 ,  H03F3/45192 ,  H03F3/4521 ,  H03F3/45475 ,  H03F2200/336 ,  H03F2200/451 ,  H03F2200/453 ,  H03F2200/456 ,  H03F2203/45241 ,  H03F2203/45318 ,  H03F2203/45356 ,  H03F2203/45366 ,  H03F2203/45466 ,  H03F2203/45641 ,  H03F2203/45702 ,  H03F2203/45704 ,  H03H7/24 ,  H03H11/04 ,  H03H11/1291 ,  H03H11/24 ,  H03H11/54 ,  H03L7/10 ,  H03L7/18 ,  H01L2924/00

摘要： An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. LC filters integrated onto the substrate in conjunction with image reject mixers provide image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. Active filters utilize multi track spiral inductors with shields to increase circuit Q. The filters incorporate a gain stage that provides improved dynamic range through the use of cross coupled auxiliary differential pair CMOS amplifiers to cancel distortion in a main linearized differential pair amplifier. Frequency planning provides additional image rejection. Local oscillator signal generation methods on chip reduce distortion. A PLL generates needed out of band LO signals. Direct synthesis generates in band LO signals. PLL VCOs are centered automatically. A differential crystal oscillator provides a frequency reference. Differential signal transmission throughout the receiver is used. ESD protection is provided by a pad ring and ESD clamping structure. Shunts utilize a gate boosting at each pin to discharge ESD build up. An IF VGA utilizes distortion cancellation achieved with cross coupled differential pair amplifiers having their Vds dynamically modified in conjunction with current steering of the differential pairs sources.

摘要翻译： 具有通道选择和图像抑制的集成接收器基本上在单个CMOS集成电路上实现。 接收机前端提供可编程衰减和可编程增益低噪声放大器。 与图像抑制混合器一起集成到衬底上的LC滤波器提供图像频率抑制。 过滤器调谐和电感Q补偿温度在芯片上执行。 有源滤波器利用具有屏蔽的多轨螺旋电感器来增加电路Q.滤波器包括增益级，其通过使用交叉耦合辅助差分对CMOS放大器来消除主线性化差分对放大器中的失真而提供改进的动态范围。 频率规划提供额外的镜像抑制。 本地振荡器信号产生方法在芯片上减少失真。 PLL产生所需的带外LO信号。 直接合成产生带内LO信号。 PLL VCO自动居中。 差分晶体振荡器提供频率参考。 使用整个接收机的差分信号传输。 ESD保护由衬垫环和ESD夹紧结构提供。 分流器利用每个引脚上的门极升压来放电ESD积聚。 IF VGA利用交叉耦合的差分对放大器实现的失真消除，其具有与差分对源的当前转向结合动态修改的V ds。

公开(公告)号：US20070075799A1

公开(公告)日：2007-04-05

申请号：US11292546

申请日：2005-12-02

申请人： Sheng-Lyang Jang ,  Shao-Hua Lee

发明人： Sheng-Lyang Jang ,  Shao-Hua Lee

IPC分类号： H03B5/12

CPC分类号： H03B5/1228 ,  H03B5/1203 ,  H03B5/1209 ,  H03B5/1243 ,  H03B5/1265

摘要： The present invention is related with a dual-band LC voltage controlled oscillator, which utilizes a substantial amount of feedback loop paths in the circuit. The circuit is a core of a substantial amount of communication ICs. The voltage controlled oscillator can provide wide-band or dual-band radio frequency generation, and it utilizes a switch controlled circuit to select one of the feedback loops in order to choose the assigned frequency band output. Generic wide-band or dual-band LC voltage controlled oscillations are obtained by switching parallel-connected capacitors or switching inductor array, in contrast, the present invention is used for switching several parallel connected feedback loops, each of which associated with an LC tank forms an oscillation frequency output. Utilizing the switch to control the feedback loop and integrating different band oscillator circuit is capable of saving chip's size and power consumption.

公开(公告)号：US07176766B2

公开(公告)日：2007-02-13

申请号：US10528254

申请日：2003-08-08

申请人： Johannes Hubertus Antonius Brekelmans

发明人： Johannes Hubertus Antonius Brekelmans

IPC分类号： H03B5/00

CPC分类号： H03B5/1228 ,  H03B5/1209 ,  H03B5/1215 ,  H03B5/1221 ,  H03B5/1243

摘要： An LC oscillator (I) comprises a cross-coupled PMOS transistor pair (Ma, Mb) coupled to a pair of capacitors (Cva, Cvb) and a pair of inductances (La, Lb). To enhance the signal amplification of the oscillator, a pair of auxiliary transistor circuits (Qa, Qb; Na, Nb) is provided which are coupled between the drain and, preferably, the source of each PMOS transistor. The capacitors (Cva, Cvb) are preferably variable capacitors and the inductances (La, Lb) are preferably connected to ground to allow a enlarged tuning voltage range.

摘要翻译： LC振荡器（I）包括耦合到一对电容器（Cva，Cvb）和一对电感（La，Lb）的交叉耦合PMOS晶体管对（Ma，Mb）。 为了增强振荡器的信号放大，提供了一对辅助晶体管电路（Qa，Qb; Na，Nb），其耦合在每个PMOS晶体管的漏极和优选地源极之间。 电容器（Cva，Cvb）优选地是可变电容器，并且电感（La，Lb）优选地连接到地，以允许扩大的调谐电压范围。

公开(公告)号：US20060238265A1

公开(公告)日：2006-10-26

申请号：US11112527

申请日：2005-04-22

申请人： Babak Soltanian ,  Herschel Ainspan ,  Daniel Friedman ,  Woogeun Rhee

发明人： Babak Soltanian ,  Herschel Ainspan ,  Daniel Friedman ,  Woogeun Rhee

IPC分类号： H03B5/08

CPC分类号： H03L7/099 ,  H03B5/1209 ,  H03B5/1228 ,  H03B5/1253 ,  H03B2201/0208 ,  H03L2207/06

摘要： A method of differentially controlling an LC voltage controlled oscillator (VCO) includes providing an LC-VCO comprising at least one inductor, measuring an inductor common voltage (CMV) output at a point along the at least one inductor, utilizing the measured inductor CMV as an input to a charge pump, and outputting from the charge pump a plurality of differential control voltages to control an output of the LC-VCO.

摘要翻译： 一种差分控制LC压控振荡器（VCO）的方法包括提供包括至少一个电感器的LC-VCO，测量沿着至少一个电感器的点处的电感器公共电压（CMV）输出，利用测量的电感器CMV作为 电荷泵的输入，并从电荷泵输出多个差分控制电压以控制LC-VCO的输出。

公开(公告)号：US07126403B2

公开(公告)日：2006-10-24

申请号：US10978972

申请日：2004-11-01

申请人： John G. Kenney, Jr. ,  Viswabharath Reddy ,  Ward Steven Titus

发明人： John G. Kenney, Jr. ,  Viswabharath Reddy ,  Ward Steven Titus

IPC分类号： G06F1/04

CPC分类号： H03B5/1228 ,  H03B5/1209 ,  H03B5/1215 ,  H03B5/1225 ,  H03B5/124 ,  H03B5/1265 ,  H03B2201/0266

摘要： A new clock driver is described for the use in the phase detector of a clock and data recovery circuit (CDR). By building a resonant LC tank, whose center frequency is similar to the clock frequency, a low power clock driver is realized. A method based upon minimizing power consumption is described for determining the value of the programmable capacitance. A programmable capacitance adjusts the center frequency of the tank so it matches the frequency of the clock and a finite state machine at startup determines the value of this programmable capacitance. A criterion for tuning the center frequency of the tank is to choose the capacitance which leads to the lowest power consumption. A low Q tank affords a reasonable compromise between power efficiency and performance in the CDR circuit.

摘要翻译： 描述了用于时钟和数据恢复电路（CDR）的相位检测器中的新的时钟驱动器。 通过建立一个谐振LC箱，其中心频率与时钟频率相似，实现了低功率时钟驱动器。 描述了基于最小化功耗的方法来确定可编程电容的值。 可编程电容可调节电容器的中心频率，使其与时钟频率相匹配，启动时的有限状态机可确定该可编程电容的值。 调整储罐中心频率的标准是选择导致最低功耗的电容。 低Q槽在CDR电路中提供功率效率和性能之间的合理折中。