Fractional frequency divider
    1.
    发明授权
    Fractional frequency divider 有权
    分数分频器

    公开(公告)号:US08963588B2

    公开(公告)日:2015-02-24

    申请号:US13215135

    申请日:2011-08-22

    申请人: Nicola Da Dalt

    发明人: Nicola Da Dalt

    IPC分类号: H03B19/00 H03L7/197

    CPC分类号: H03L7/1976

    摘要: An oscillator may output phased signals to a phase interpolator which is to generate an adjustable output clock signal having a phase offset relative to at least one of the phased signals received from the oscillator. A divider may then divide the frequency of the output signal generated by the phase interpolator by an integer factor.

    摘要翻译: 振荡器可将相控信号输出到相位内插器,该相位内插器将产生相对于从振荡器接收到的相控信号中的至少一个的相位偏移的可调输出时钟信号。 然后,分频器可以将由相位插值器产生的输出信号的频率除以整数因子。

    Method and device for stabilizing a transfer function of a digital phase locked loop
    2.
    发明授权
    Method and device for stabilizing a transfer function of a digital phase locked loop 有权
    稳定数字锁相环传递函数的方法和装置

    公开(公告)号:US07358820B2

    公开(公告)日:2008-04-15

    申请号:US11477578

    申请日:2006-06-29

    申请人: Nicola Da Dalt

    发明人: Nicola Da Dalt

    IPC分类号: H03L7/00

    摘要: In a method for stabilizing a transfer function of a digital phase locked loop a random digital signal is fed into the phase locked loop. The phase locked loop comprises the transfer function and a phase locked loop gain which changes with time due to disturbances and the random digital signal comprises a predetermined variance. The transfer function depends from the phase locked loop gain. A cross correlation function is generated by cross correlating a signal of the phase locked loop with the random signal and an impulse response is estimated between the random signal and the signal of the phase locked loop by means of the cross correlation function and the predetermined variance of the random signal. The transfer function of the phase locked loop is set in dependence on the estimated impulse response.

    摘要翻译: 在稳定数字锁相环的传递函数的方法中,将随机数字信号馈送到锁相环。 锁相环包括由于干扰而随时间变化的传递函数和锁相环增益,并且随机数字信号包括预定的方差。 传递函数取决于锁相环增益。 通过将锁相环的信号与随机信号相互相关来产生互相关函数,并且通过互相关函数和相关函数和相关函数的预定方差在随机信号和锁相环的信号之间估计脉冲响应 随机信号。 根据估计的脉冲响应来设定锁相环的传递函数。

    Method and device for generating a clock signal using a phase difference signal and a feedback signal
    3.
    发明授权
    Method and device for generating a clock signal using a phase difference signal and a feedback signal 有权
    使用相位差信号和反馈信号来产生时钟信号的方法和装置

    公开(公告)号:US07282999B2

    公开(公告)日:2007-10-16

    申请号:US11194770

    申请日:2005-08-01

    IPC分类号: H03L7/085 H03L7/087

    摘要: A method and a device for generating a clock signal (Fout) are provided, wherein a digital phase difference signal (X) is formed depending on a phase difference between a reference clock signal (Fin) and a feedback signal (Ffb) derived from the clock signal (Fout) and wherein the digital phase difference signal (X) is digitally filtered, in order to form a digital filtered phase difference signal (U). A digitally controlled oscillator (5) is activated by a digital control signal dependent on the digital filtered phase difference signal (U) to generate the clock signal (Fout). With a device of this kind clock signals with frequencies in the gigahertz range can be generated with a minimum of analog circuit parts.

    摘要翻译: 提供了一种用于产生时钟信号(F OUT)的方法和装置,其中根据参考时钟信号(F SUB)之间的相位差形成数字相位差信号(X) 并且其中数字相位差信号(X)被数字滤波,并且其中数字相位差信号(X)被<! - SIPO - ,以形成数字滤波相位差信号(U)。 数字控制振荡器(5)由取决于数字滤波相位差信号(U)的数字控制信号激活,以产生时钟信号(F OUT)。 使用这种类型的器件,可以使用最小的模拟电路部分来生成千兆赫兹范围内的频率的时钟信号。

    Method and device for controlling an oscillator
    4.
    发明申请
    Method and device for controlling an oscillator 审中-公开
    用于控制振荡器的方法和装置

    公开(公告)号:US20050077970A1

    公开(公告)日:2005-04-14

    申请号:US10920707

    申请日:2004-08-18

    CPC分类号: H03L7/10 H03L7/18 H03L2207/06

    摘要: A method and a device for controlling an oscillator (1) are proposed, wherein a first control signal (b) is generated depending on an output signal (e) of the oscillator (1) and on a first reference signal (a), and a second control signal (d) is generated depending on the first control signal (b) and on a second reference signal (c), and wherein the oscillator (1) is subjected to the first control signal (b) and to the second control signal (d) and generates the output signal (e) with a frequency dependent on the first control signal (b) and on the second control signal (d). A low-noise phase locked loop with a large possible frequency range can be realised by such a method and such a device.

    摘要翻译: 提出了一种用于控制振荡器(1)的方法和装置,其中根据振荡器(1)的输出信号(e)和第一参考信号(a)产生第一控制信号(b),以及 根据第一控制信号(b)和第二参考信号(c)产生第二控制信号(d),并且其中振荡器(1)经受第一控制信号(b)和第二控制信号 信号(d),并产生具有取决于第一控制信号(b)的频率和第二控制信号(d)的输出信号(e)。 通过这种方法和这种装置可以实现具有可能的频率范围很大的低噪声锁相环。

    Circuit with noise shaper
    7.
    发明授权
    Circuit with noise shaper 有权
    电路与噪音整形器

    公开(公告)号:US08076978B2

    公开(公告)日:2011-12-13

    申请号:US12270584

    申请日:2008-11-13

    IPC分类号: H03L7/085 H03L7/089

    CPC分类号: H03L7/16 H03L2207/50

    摘要: In an embodiment, a circuit comprising an oscillator is provided. The oscillator is controlled based on a feedback value and an input reference value. The feedback value or the reference value or both are generated using noise shaping.

    摘要翻译: 在一个实施例中,提供了包括振荡器的电路。 基于反馈值和输入参考值来控制振荡器。 使用噪声整形产生反馈值或参考值或两者。

    Circuit with multiphase oscillator
    8.
    发明授权
    Circuit with multiphase oscillator 有权
    电路与多相振荡器

    公开(公告)号:US07847643B2

    公开(公告)日:2010-12-07

    申请号:US12267277

    申请日:2008-11-07

    申请人: Nicola Da Dalt

    发明人: Nicola Da Dalt

    IPC分类号: H03B27/00

    摘要: In an embodiment, a circuit is provided comprising a multi-phase oscillator configured to output a plurality of output signals having the same frequency and different phase offsets. A feedback value is generated based on at least two of said output signals. A reference value is generated based on a reference clock and a predetermined value. The reference value and the feedback value are combined.

    摘要翻译: 在一个实施例中,提供一种电路,其包括配置成输出具有相同频率和不同相位偏移的多个输出信号的多相位振荡器。 基于至少两个所述输出信号产生反馈值。 基于参考时钟和预定值生成参考值。 参考值和反馈值组合。

    Cell array with mismatch reduction
    9.
    发明授权
    Cell array with mismatch reduction 有权
    具有失配减少的单元阵列

    公开(公告)号:US06911930B1

    公开(公告)日:2005-06-28

    申请号:US10737728

    申请日:2003-12-15

    IPC分类号: H03M1/06 H03M1/76 H03M1/12

    CPC分类号: H03M1/0648 H03M1/765

    摘要: A cell array has a plurality of cell elements integrated in a wafer in a bidimensional cell matrix, wherein each integrated cell element comprises a mismatch between its actual physical property and a nominal property value. The mismatch of each cell element is a function of the distance of the respective cell element to a center of the cell array having a bidimensional mismatch distribution which is circular symmetric. The cell elements are connected in series in a wiring pattern along the circular symmetric mismatch distribution of the cell array to reduce an accumulated mismatch.

    摘要翻译: 单元阵列具有集成在二维单元矩阵中的晶片中的多个单元元件,其中每个集成单元元件包括其实际物理特性与标称特性值之间的不匹配。 每个单元元件的不匹配是各个单元元件与具有圆形对称的二维不匹配分布的单元阵列的中心的距离的函数。 电池元件沿着电池阵列的圆形对称不匹配分布以布线图案串联连接,以减少累积的不匹配。

    Programmable fractional frequency divider
    10.
    发明授权
    Programmable fractional frequency divider 有权
    可编程分数分频器

    公开(公告)号:US06738449B2

    公开(公告)日:2004-05-18

    申请号:US10153365

    申请日:2002-05-22

    申请人: Nicola Da Dalt

    发明人: Nicola Da Dalt

    IPC分类号: H03K2100

    CPC分类号: H03L7/18 H03K23/68 H03L7/081

    摘要: The invention features a fractional frequency divider including a phase selection device where mutually phase-shifted signals are alternately switched through to a phase output, at the input of the phase selection device; and a control device for selecting individual phases where the control device changes the mutually phase-shifted signals.

    摘要翻译: 本发明的特征在于包括相位选择装置的分数分频器,其中相位选择装置在相位选择装置的输入处交替切换到相位输出; 以及用于选择控制装置改变相互相移的信号的各个相位的控制装置。