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    Method and device for transmitting outgoing useful signals and an outgoing clock signal
    3.
    发明授权
    Method and device for transmitting outgoing useful signals and an outgoing clock signal 有权
    用于发送输出有用信号和输出时钟信号的方法和装置

    公开(公告)号：US08125812B2

    公开(公告)日：2012-02-28

    申请号：US12058899

    申请日：2008-03-31

    Applicant: Martin Streibl ,  Peter Gregorius ,  Ralf Schledz

    Inventor： Martin Streibl ,  Peter Gregorius ,  Ralf Schledz

    IPC: G11C5/02

    CPC classification number: G11C7/22 ,  G06F1/10 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/222

    Abstract: Method and device for transmitting outgoing useful signals and an outgoing clock signal. Useful signals and a clock signal are transmitted from a transmitter via a first line pair and a second line pair to a receiver. A first useful signal is transmitted in the form of a modulated difference between the electrical potentials of the first line pair. A second useful signal is transmitted in the form of a modulated difference between the electrical potentials of the second line pair. The clock signal is transmitted in the form of a modulated difference between the average value of the potentials of the first line pair and the average value of the potentials of the second line pair.

    Abstract translation: 用于发送输出有用信号和输出时钟信号的方法和装置。 有用的信号和时钟信号从发射机经由第一线对和第二线对发射到接收机。 第一有用信号以第一线对的电位之间的调制差的形式发送。 第二有用信号以第二线对的电位之间的调制差的形式传输。 时钟信号以第一线对的电位的平均值与第二线对的电位的平均值之间的调制差的形式发送。

    Memory device and memory system comprising a memory device and a memory control device
    4.
    发明授权
    Memory device and memory system comprising a memory device and a memory control device 有权
    存储器件和存储器系统，包括存储器件和存储器控制器件

    公开(公告)号：US08031539B2

    公开(公告)日：2011-10-04

    申请号：US12248759

    申请日：2008-10-09

    Applicant: Peter Gregorius

    Inventor： Peter Gregorius

    IPC: G11C7/00

    CPC classification number: G11C5/00 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076

    Abstract: In an embodiment, a memory device comprises a clock generating unit being configured to generate a read clock signal, the clock generating unit being connected to a first clock signal contact configured to send the read clock signal, and the clock generating unit being connected to data signal contacts being configured to send data signals, the memory device being configured to send the data signals in a phase and frequency accurate (source synchronous) manner with regard to the read clock signal.

    Abstract translation: 在一个实施例中，存储器件包括时钟产生单元，其被配置为产生读取时钟信号，所述时钟产生单元连接到被配置为发送读取时钟信号的第一时钟信号触点，并且所述时钟产生单元连接到数据 信号触点被配置为发送数据信号，所述存储器件被配置为相对于读时钟信号以相位和频率精确（源同步）方式发送数据信号。

    Training connections in a memory arrangement
    5.
    发明授权
    Training connections in a memory arrangement 有权
    训练连接在内存安排

    公开(公告)号：US07908232B2

    公开(公告)日：2011-03-15

    申请号：US11844791

    申请日：2007-08-24

    Applicant: Peter Gregorius

    Inventor： Peter Gregorius

    IPC: G06F15/18

    CPC classification number: G06F13/1684

    Abstract: A method of training connections in a memory arrangement includes training a connection between a memory section and a receiver portion of a controller for controlling the memory arrangement before or simultaneously with a training of essentially all other connections between elements of the memory arrangement that are to be trained.

    Abstract translation: 训练存储器装置中的连接的方法包括训练存储器部分和控制器的接收器部分之间的连接，用于在存储器装置的元件之间的基本上所有其他连接的训练之前或同时进行控制， 训练有素

    Bus Termination System and Method
    8.
    发明申请
    Bus Termination System and Method 有权
    总线终端系统和方法

    公开(公告)号：US20100030934A1

    公开(公告)日：2010-02-04

    申请号：US12185472

    申请日：2008-08-04

    Applicant: Michael Bruennert ,  Peter Gregorius ,  Georg Braun ,  Andreas Gaertner ,  Hermann Ruckerbauer ,  George Alexander ,  Johannes Stecker

    Inventor： Michael Bruennert ,  Peter Gregorius ,  Georg Braun ,  Andreas Gaertner ,  Hermann Ruckerbauer ,  George Alexander ,  Johannes Stecker

    IPC: G06F13/38 ,  G06F3/00

    CPC classification number: G06F13/4086

    Abstract: A memory system includes a number of integrated circuit chips coupled to a bus. Each of the integrated circuit chips has an input/output node coupled to the bus, the input/output node having a programmable on-die termination resistor. The input/output node of one of the integrated circuit chips is accessed via the bus. The programmable on-die termination resistor of each of the integrated circuit chips is independently set to a termination resistance. The termination resistance is determined by a transaction type and which of the plurality memory devices is being accessed, which information can be transmitted over a separate transmission control bus.

    Abstract translation: 存储器系统包括耦合到总线的多个集成电路芯片。 每个集成电路芯片具有耦合到总线的输入/输出节点，该输入/输出节点具有可编程的片上终端电阻器。 通过总线访问集成电路芯片之一的输入/输出节点。 每个集成电路芯片的可编程片上终端电阻独立地设置为终端电阻。 终端电阻由交易类型和正在被访问的多个存储器件中的哪一个确定，哪些信息可以通过单独的传输控制总线传输。

    Method of transferring signals between a memory device and a memory controller
    9.
    发明授权
    Method of transferring signals between a memory device and a memory controller 有权
    在存储器件和存储器控制器之间传送信号的方法

    公开(公告)号：US07587655B2

    公开(公告)日：2009-09-08

    申请号：US11259376

    申请日：2005-10-26

    Applicant: Paul Wallner ,  Andre Schaefer ,  Thomas Hein ,  Peter Gregorius

    Inventor： Paul Wallner ,  Andre Schaefer ,  Thomas Hein ,  Peter Gregorius

    IPC: G11C29/00

    CPC classification number: G11C8/18

    Abstract: Method and apparatus for communication (e.g., transmitting and/or receiving) command, address and data signals from a memory device to a memory controller or vice versa. The data signals are transferred with a first rate and command signals and/or address signals are transferred with a second rate lower than a first rate. Additionally or alternatively a command sequence code identifying a command sequence from a predefined group of command sequences is transferred with the first or with the second rate.

    Abstract translation: 用于从存储器设备到存储器控制器的通信（例如，发送和/或接收）命令，地址和数据信号的方法和装置，反之亦然。 数据信号以第一速率传送，命令信号和/或地址信号以低于第一速率的第二速率传送。 附加地或替代地，从预定义的命令序列组识别命令序列的命令序列代码以第一速率或第二速率传送。

    Device for the production of standard-compliant signals
    10.
    发明授权
    Device for the production of standard-compliant signals 有权
    用于生产标准兼容信号的设备

    公开(公告)号：US07474876B2

    公开(公告)日：2009-01-06

    申请号：US10916776

    申请日：2004-08-12

    Applicant: Jörg Bonhaus ,  Thomas Duda ,  Lajos Gazsi ,  Peter Gregorius

    Inventor： Jörg Bonhaus ,  Thomas Duda ,  Lajos Gazsi ,  Peter Gregorius

    IPC: H04B17/00 ,  H03C1/62

    CPC classification number: H04L27/368

    Abstract: A device for the production of standard compliant signals, for example pulse-type signals in a telecommunication network, serves the production and adaptation and/or pre-distortion of signals with a certain signal form, which is defined dependent on a standard signal form specified in a standard. The device comprises signal generation means (10) for the production of the signals with a certain signal form and signal adjustment means (20) for the adaptation or pre-distortion of the signals. The signal generation means (10) according to the invention are digitally realized, by using a programmable shift register (14), which contains multipliers specified by the standard signal form for multiplication with a digital input signal (1). The signal adjustment means (20) comprise substantially scalable digital filter arrangements in the form of a serial connection of digital filters (22) with a downstream multiplexer (24). Moreover, the invention provides attenuating means (50) for attenuation of the signal dependent on the characteristics of the telecommunication channel.

    Abstract translation: 用于生产标准兼容信号（例如电信网络中的脉冲型信号）的装置用于以特定信号形式产生和适应和/或预失真信号，该特定信号形式取决于指定的标准信号形式 在一个标准。 该装置包括用于产生具有特定信号形式的信号的信号产生装置（10）和用于信号的自适应或预失真的信号调节装置（20）。 根据本发明的信号产生装置（10）通过使用可编程移位寄存器（14）进行数字实现，该可编程移位寄存器（14）包含用于与数字输入信号（1）相乘的标准信号形式指定的乘法器。 信号调节装置（20）包括数字滤波器（22）与下游多路复用器（24）的串行连接形式的基本上可伸缩的数字滤波器装置。 此外，本发明提供衰减装置（50），用于根据电信信道的特性衰减信号。

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