公开(公告)号：US09444400B2

公开(公告)日：2016-09-13

申请号：US14666084

申请日：2015-03-23

Applicant: QUALCOMM Incorporated

Inventor： Mazhareddin Taghivand ,  Keplin Victor Johansen

IPC: H03B5/12

CPC classification number: H03B5/1262 ,  H03B5/1203 ,  H03B5/1206 ,  H03B5/1209 ,  H03B5/1228 ,  H03B5/1243 ,  H03B5/1265 ,  H03B5/129

Abstract: Systems and methods for biasing frequency oscillators to minimize phase noise are disclosed. The system may comprise a tank circuit having an inductor, at least a first coupling capacitor and a second coupling capacitor. The system may further comprise a varactor circuit electrically connected to the first coupling capacitor and the second coupling capacitor. The system may further comprise at least one first metal oxide semiconductor (MOS) device electrically connected in shunt with the tank circuit and a bias voltage. The at least one first MOS device may be electrically connected to a first gate bias voltage configured to bias the at least one first MOS device such that a first gate-to-source voltage of the at least one first MOS device remains below the first threshold voltage.

Abstract translation: 公开了用于偏置频率振荡器以最小化相位噪声的系统和方法。 该系统可以包括具有电感器，至少第一耦合电容器和第二耦合电容器的振荡电路。 该系统还可以包括电连接到第一耦合电容器和第二耦合电容器的变容二极管电路。 该系统可以进一步包括至少一个第一金属氧化物半导体（MOS）器件，其电连接到与谐振电路并联的偏置电压。 至少一个第一MOS器件可以电连接到第一栅极偏置电压，其被配置为偏置至少一个第一MOS器件，使得至少一个第一MOS器件的第一栅极至源极电压保持低于第一阈值 电压。

公开(公告)号：US09490826B1

公开(公告)日：2016-11-08

申请号：US14829723

申请日：2015-08-19

Applicant: QUALCOMM Incorporated

Inventor： Cheng-Han Wang ,  Keplin Victor Johansen ,  Jeongsik Yang ,  Justin Phelps Black

IPC: H03L7/06 ,  H03L7/099

CPC classification number: H03L7/099 ,  H03L7/00

Abstract: Methods and apparatus for synchronizing dividers in different LO paths using pulse swallowing. One example apparatus generally includes a first path having a first frequency divider configured to generate a first divided signal from a first periodic signal; a second path having a second frequency divider configured to generate a second divided signal from a second periodic signal; a phase detector configured to compare phases of a first sensing signal based on the first divided signal and a second sensing signal based on the second divided signal and to generate a first trigger signal if the first and second sensing signals are out-of-phase; and a first pulse suppressor configured to suppress a pulse of the first periodic signal for at least one cycle in response to the first trigger signal to adjust a phase of the first divided signal.

Abstract translation: 使用脉冲吞咽在不同LO路径中同步分频器的方法和装置。 一个示例性装置通常包括具有第一分频器的第一路径，其被配置为从第一周期性信号产生第一分频信号; 第二路径，具有被配置为从第二周期信号产生第二分频信号的第二分频器; 相位检测器，被配置为基于第一分频信号和第二感测信号基于第二分频信号比较第一感测信号的相位，并且如果第一和第二感测信号是异相的，则产生第一触发信号; 以及第一脉冲抑制器，被配置为响应于所述第一触发信号来抑制所述第一周期信号的脉冲至少一个周期，以调整所述第一分频信号的相位。

公开(公告)号：US20170063383A1

公开(公告)日：2017-03-02

申请号：US14838204

申请日：2015-08-27

Applicant: QUALCOMM Incorporated

Inventor： Jeongsik Yang ,  Yashar Rajavi ,  Keplin Victor Johansen ,  Ara Bicakci

IPC: H03L7/081 ,  H03L7/099 ,  H04B7/06 ,  H04W56/00 ,  H04B7/04

CPC classification number: H03L7/081 ,  H03L7/0807 ,  H03L7/099 ,  H04B7/0452 ,  H04W56/0015

Abstract: This disclosure provides a device and method for synchronizing local oscillator (LO) chains. The method can include sampling first I-data and first Q-data to generate first sampled I-data and first sampled Q-data based on a sampling clock signal. The method can also include calibrating the sampling clock signal based on the first sampled I-data and the first sampled Q-data to generate a first calibrated sampling clock signal, the first calibrated sampling clock signal indicating an optimal sample position to sample the first I-data and the first Q-data. The method can also include synchronizing a phase of the first LO chain and a second LO chain based on the first calibrated sampling clock signal.

Abstract translation: 本公开提供了一种用于同步本地振荡器（LO）链的装置和方法。 该方法可以包括对第一I数据和第一Q数据进行采样，以便基于采样时钟信号产生第一采样的I数据和第一采样的Q数据。 该方法还可以包括基于第一采样的I数据和第一采样的Q数据来校准采样时钟信号以产生第一校准的采样时钟信号，第一校准采样时钟信号指示最佳采样位置以对第一I 数据和第一个Q数据。 该方法还可以包括基于第一校准采样时钟信号来同步第一LO链和第二LO链的相位。

公开(公告)号：US20160204738A1

公开(公告)日：2016-07-14

申请号：US14666084

申请日：2015-03-23

Applicant: QUALCOMM Incorporated

Inventor： Mazhareddin Taghivand ,  Keplin Victor Johansen

IPC: H03B5/12

CPC classification number: H03B5/1262 ,  H03B5/1203 ,  H03B5/1206 ,  H03B5/1209 ,  H03B5/1228 ,  H03B5/1243 ,  H03B5/1265 ,  H03B5/129

Abstract: Systems and methods for biasing frequency oscillators to minimize phase noise are disclosed. The system may comprise a tank circuit having an inductor, at least a first coupling capacitor and a second coupling capacitor. The system may further comprise a varactor circuit electrically connected to the first coupling capacitor and the second coupling capacitor. The system may further comprise at least one first metal oxide semiconductor (MOS) device electrically connected in shunt with the tank circuit and a bias voltage. The at least one first MOS device may be electrically connected to a first gate bias voltage configured to bias the at least one first MOS device such that a first gate-to-source voltage of the at least one first MOS device remains below the first threshold voltage.

Abstract translation: 公开了用于偏置频率振荡器以最小化相位噪声的系统和方法。 该系统可以包括具有电感器，至少第一耦合电容器和第二耦合电容器的振荡电路。 该系统还可以包括电连接到第一耦合电容器和第二耦合电容器的变容二极管电路。 该系统可以进一步包括至少一个第一金属氧化物半导体（MOS）器件，其电连接到与谐振电路并联的偏置电压。 至少一个第一MOS器件可以电连接到第一栅极偏置电压，其被配置为偏置至少一个第一MOS器件，使得至少一个第一MOS器件的第一栅极至源极电压保持低于第一阈值 电压。