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    Data accessing method, memory control circuit unit and memory storage device
    1.
    发明授权
    Data accessing method, memory control circuit unit and memory storage device 有权

    公开(公告)号：US11467773B2

    公开(公告)日：2022-10-11

    申请号：US17177214

    申请日：2021-02-17

    Applicant: PHISON ELECTRONICS CORP.

    Inventor： Wei-Cheng Li ,  Yu-Chung Shen ,  Nien-Hung Lin

    IPC: G06F12/00 ,  G06F3/06 ,  G06F12/10 ,  G06F11/10

    Abstract: A data accessing method, a memory control circuit unit, and a memory storage device are provided. The data accessing method includes the following steps. A reading command is received from a host system, in which the reading command instructs to read a first logical address, the first logical address is mapped to a first physical programming unit, and the first physical programming unit corresponds to a first physical erasing unit. A first data is generated after receiving the reading command, and the first data is written to a second physical programming unit included in the first physical erasing unit. A second data stored in the first physical programming unit is read after the first data is written, so as to respond to the reading command.

    MEMORY CONTROL CIRCUIT UNIT, MEMORY STORAGE DEVICE AND PARAMETER UPDATING METHOD
    4.
    发明公开
    MEMORY CONTROL CIRCUIT UNIT, MEMORY STORAGE DEVICE AND PARAMETER UPDATING METHOD 审中-公开

    公开(公告)号：US20240345764A1

    公开(公告)日：2024-10-17

    申请号：US18332771

    申请日：2023-06-12

    Applicant: PHISON ELECTRONICS CORP.

    Inventor： Wei-Cheng Li ,  Ping-Cheng Chen ,  Yu-Chung Shen ,  Jia-Li Xu

    IPC: G06F3/06

    CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

    Abstract: A memory control circuit unit, a memory storage device, and a parameter updating method are disclosed. The memory control circuit unit includes a host interface, a memory interface, and a memory management circuit. The memory interface is configured to be coupled to a rewritable non-volatile memory module. The memory management circuit is configured to detect system status and activate an interface parameter updating operation in response to the system status meeting a target condition. The memory management circuit is further configured to update at least one interface parameter used by at least one of the memory interface and the rewritable non-volatile memory module during the interface parameter updating operation.

    NON-VOLATILE MEMORY STORAGE APPARATUS, MEMORY CONTROLLER AND DATA STORING METHOD
    5.
    发明申请
    NON-VOLATILE MEMORY STORAGE APPARATUS, MEMORY CONTROLLER AND DATA STORING METHOD 审中-公开
    非易失存储器，存储控制器和数据存储方法

    公开(公告)号：US20140297936A1

    公开(公告)日：2014-10-02

    申请号：US14306240

    申请日：2014-06-17

    Applicant: PHISON ELECTRONICS CORP.

    Inventor： Hsiang-Hsiung Yu ,  Ta-Chuan Wei ,  Yun-Chieh Chen ,  Yu-Chung Shen

    IPC: G06F12/02

    CPC classification number: G06F12/00 ,  G06F3/0614 ,  G06F3/0656 ,  G06F3/0658 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/7203 ,  G06F2212/7207 ,  G11C5/143 ,  G11C16/10 ,  G11C16/30 ,  Y02D10/13

    Abstract: A non-volatile memory storage apparatus having a connector, an energy storage circuit, a power regulator and supply circuit, a non-volatile memory module, a memory controller and a buffer memory is provided. The power regulator and supply circuit is configured for transforming an output voltage from the energy storage circuit into a first voltage used for the non-volatile memory module and a second voltage used for the memory controller and the buffer memory. The memory controller is configured for writing data stored temporarily in the buffer memory into the non-volatile memory module with a special writing mode when receiving a detecting signal indicating that an input voltage is continuously smaller than a predetermined voltage for a predetermined period or receiving a detecting signal indicating that an inactive status of the connector or receiving a suspend mode signal, a warm reset signal or a hot reset signal from a host system.

    Abstract translation: 提供一种具有连接器，能量存储电路，功率调节器和电源电路，非易失性存储器模块，存储器控制器和缓冲存储器的非易失性存储器存储装置。 功率调节器和电源电路被配置为将来自能量存储电路的输出电压变换为用于非易失性存储器模块的第一电压和用于存储器控制器和缓冲存储器的第二电压。 存储器控制器被配置为当接收到指示输入电压连续小于预定电压达预定时间段的检测信号或者接收到一个或多个存储器时，将临时存储在缓冲存储器中的数据以特殊写入模式写入非易失性存储器模块 检测信号，指示连接器的不活动状态或接收来自主机系统的挂起模式信号，热复位信号或热复位信号。

    Non-volatile memory storage apparatus, memory controller and data storing method
    7.
    发明授权
    Non-volatile memory storage apparatus, memory controller and data storing method 有权
    非易失性存储器存储装置，存储器控制器和数据存储方法

    公开(公告)号：US08837248B2

    公开(公告)日：2014-09-16

    申请号：US13772363

    申请日：2013-02-21

    Applicant: Phison Electronics Corp.

    Inventor： Hsiang-Hsiung Yu ,  Ta-Chuan Wei ,  Yun-Chieh Chen ,  Yu-Chung Shen

    IPC: G11C16/10 ,  G06F12/02 ,  G06F3/06 ,  G11C5/14 ,  G11C16/30 ,  G06F12/00

    CPC classification number: G06F12/00 ,  G06F3/0614 ,  G06F3/0656 ,  G06F3/0658 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/7203 ,  G06F2212/7207 ,  G11C5/143 ,  G11C16/10 ,  G11C16/30 ,  Y02D10/13

    Abstract: A non-volatile memory storage apparatus having a connector, an energy storage circuit, a power regulator and supply circuit, a non-volatile memory module, a memory controller and a buffer memory is provided. The power regulator and supply circuit is configured for transforming an output voltage from the energy storage circuit into a first voltage used for the non-volatile memory module and a second voltage used for the memory controller and the buffer memory. The memory controller is configured for writing data stored temporarily in the buffer memory into the non-volatile memory module with a special writing mode when receiving a detecting signal indicating that an input voltage is continuously smaller than a predetermined voltage for a predetermined period or receiving a detecting signal indicating that an inactive status of the connector or receiving a suspend mode signal, a warm reset signal or a hot reset signal from a host system.

    Abstract translation: 提供一种具有连接器，能量存储电路，功率调节器和电源电路，非易失性存储器模块，存储器控制器和缓冲存储器的非易失性存储器存储装置。 功率调节器和电源电路被配置为将来自能量存储电路的输出电压变换为用于非易失性存储器模块的第一电压和用于存储器控制器和缓冲存储器的第二电压。 存储器控制器被配置为当接收到指示输入电压连续小于预定电压达预定时间段的检测信号或者接收到一个或多个存储器时，将临时存储在缓冲存储器中的数据以特殊写入模式写入非易失性存储器模块 检测信号，指示连接器的不活动状态或接收来自主机系统的挂起模式信号，热复位信号或热复位信号。

    DATA ACCESSING METHOD, MEMORY CONTROL CIRCUIT UNIT AND MEMORY STORAGE DEVICE
    10.
    发明申请
    DATA ACCESSING METHOD, MEMORY CONTROL CIRCUIT UNIT AND MEMORY STORAGE DEVICE 有权

    公开(公告)号：US20220229592A1

    公开(公告)日：2022-07-21

    申请号：US17177214

    申请日：2021-02-17

    Applicant: PHISON ELECTRONICS CORP.

    Inventor： Wei-Cheng Li ,  Yu-Chung Shen ,  Nien-Hung Lin

    IPC: G06F3/06 ,  G06F12/10 ,  G06F11/10

    Abstract: A data accessing method, a memory control circuit unit, and a memory storage device are provided. The data accessing method includes the following steps. A reading command is received from a host system, in which the reading command instructs to read a first logical address, the first logical address is mapped to a first physical programming unit, and the first physical programming unit corresponds to a first physical erasing unit. A first data is generated after receiving the reading command, and the first data is written to a second physical programming unit included in the first physical erasing unit. A second data stored in the first physical programming unit is read after the first data is written, so as to respond to the reading command.

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