公开(公告)号：US12008239B1

公开(公告)日：2024-06-11

申请号：US18151470

申请日：2023-01-09

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei-Cheng Li ,  Ping-Cheng Chen ,  Yu-Chung Shen ,  Jia-Li Xu

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0659 ,  G06F3/0679

Abstract: A memory management method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: sending an erase command sequence configured to erase a first physical erasing unit in a rewritable non-volatile memory module; and sending a write command sequence configured to perform a dummy write operation on a second physical erasing unit in the rewritable non-volatile memory module with correspondence to the erasing of the first physical erasing unit. The dummy write operation is configured to store dummy data to the second physical erasing unit.

公开(公告)号：US20240345764A1

公开(公告)日：2024-10-17

申请号：US18332771

申请日：2023-06-12

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei-Cheng Li ,  Ping-Cheng Chen ,  Yu-Chung Shen ,  Jia-Li Xu

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: A memory control circuit unit, a memory storage device, and a parameter updating method are disclosed. The memory control circuit unit includes a host interface, a memory interface, and a memory management circuit. The memory interface is configured to be coupled to a rewritable non-volatile memory module. The memory management circuit is configured to detect system status and activate an interface parameter updating operation in response to the system status meeting a target condition. The memory management circuit is further configured to update at least one interface parameter used by at least one of the memory interface and the rewritable non-volatile memory module during the interface parameter updating operation.

公开(公告)号：US20240184449A1

公开(公告)日：2024-06-06

申请号：US18151470

申请日：2023-01-09

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei-Cheng Li ,  Ping-Cheng Chen ,  Yu-Chung Shen ,  Jia-Li Xu

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0659 ,  G06F3/0679

Abstract: A memory management method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: sending an erase command sequence configured to erase a first physical erasing unit in a rewritable non-volatile memory module; and sending a write command sequence configured to perform a dummy write operation on a second physical erasing unit in the rewritable non-volatile memory module with correspondence to the erasing of the first physical erasing unit. The dummy write operation is configured to store dummy data to the second physical erasing unit.

公开(公告)号：US20240086109A1

公开(公告)日：2024-03-14

申请号：US17967884

申请日：2022-10-17

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei-Cheng Li ,  Yu-Chung Shen ,  Jia-Li Xu ,  Ping-Cheng Chen

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0652 ,  G06F3/0679

Abstract: A data writing method, a memory storage device, and a memory control circuit unit are provided. The method includes: receiving a write command from a host system, and the write command including first data; checking a status of a first physical programming unit in a first physical erasing unit; in response to the status of the first physical programming unit being a first status, sending a first command sequence to a rewritable non-volatile memory module, and the first command sequence being configured to instruct the rewritable non-volatile memory module to store at least part of the first data to the first physical programming unit.