公开(公告)号：US09760509B2

公开(公告)日：2017-09-12

申请号：US14480643

申请日：2014-09-09

Applicant: PHISON ELECTRONICS CORP.

Inventor： Hsiang-Hsiung Yu ,  Yuan-Cheng Chang ,  Wei-Cheng Wu

IPC: G06F3/06 ,  G06F13/16

CPC classification number: G06F13/1673

Abstract: A memory storage device including a first and a second connection interface units, a memory control circuit unit and an interfacing circuit is provided. The first connection interface unit and the second connection interface unit are electrically connected to an input/output channel of the memory control circuit unit. The interfacing circuit is disposed between the memory control circuit unit and at least one of the first and the second connection interface units. The interfacing circuit is configured to provide determination information of an electrically connecting configuration between at least one host system and the at least one of the first and the second connection interface units. The memory control circuit unit is configured to provide different operation functions to the at least one host system based on the determination information.

公开(公告)号：US08837248B2

公开(公告)日：2014-09-16

申请号：US13772363

申请日：2013-02-21

Applicant: Phison Electronics Corp.

Inventor： Hsiang-Hsiung Yu ,  Ta-Chuan Wei ,  Yun-Chieh Chen ,  Yu-Chung Shen

IPC: G11C16/10 ,  G06F12/02 ,  G06F3/06 ,  G11C5/14 ,  G11C16/30 ,  G06F12/00

CPC classification number: G06F12/00 ,  G06F3/0614 ,  G06F3/0656 ,  G06F3/0658 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/7203 ,  G06F2212/7207 ,  G11C5/143 ,  G11C16/10 ,  G11C16/30 ,  Y02D10/13

Abstract: A non-volatile memory storage apparatus having a connector, an energy storage circuit, a power regulator and supply circuit, a non-volatile memory module, a memory controller and a buffer memory is provided. The power regulator and supply circuit is configured for transforming an output voltage from the energy storage circuit into a first voltage used for the non-volatile memory module and a second voltage used for the memory controller and the buffer memory. The memory controller is configured for writing data stored temporarily in the buffer memory into the non-volatile memory module with a special writing mode when receiving a detecting signal indicating that an input voltage is continuously smaller than a predetermined voltage for a predetermined period or receiving a detecting signal indicating that an inactive status of the connector or receiving a suspend mode signal, a warm reset signal or a hot reset signal from a host system.

Abstract translation: 提供一种具有连接器，能量存储电路，功率调节器和电源电路，非易失性存储器模块，存储器控制器和缓冲存储器的非易失性存储器存储装置。 功率调节器和电源电路被配置为将来自能量存储电路的输出电压变换为用于非易失性存储器模块的第一电压和用于存储器控制器和缓冲存储器的第二电压。 存储器控制器被配置为当接收到指示输入电压连续小于预定电压达预定时间段的检测信号或者接收到一个或多个存储器时，将临时存储在缓冲存储器中的数据以特殊写入模式写入非易失性存储器模块 检测信号，指示连接器的不活动状态或接收来自主机系统的挂起模式信号，热复位信号或热复位信号。

公开(公告)号：US09155189B1

公开(公告)日：2015-10-06

申请号：US14297646

申请日：2014-06-06

Applicant: PHISON ELECTRONICS CORP.

Inventor： Yun-Chieh Chen ,  Shih-Kung Lin ,  Ta-Chuan Wei ,  Hsiang-Hsiung Yu

IPC: H01L23/14 ,  H01L23/522 ,  H05K1/02 ,  G11C5/02 ,  H05K1/11 ,  H01R13/66 ,  H01R13/6581

CPC classification number: H05K1/0219 ,  H01L23/14 ,  H01L23/5225 ,  H01L2924/0002 ,  H01R13/6594 ,  H01R13/6658 ,  H01R24/62 ,  H05K1/0224 ,  H05K1/0225 ,  H05K1/0227 ,  H05K3/46 ,  H05K2201/0723 ,  H01L2924/00

Abstract: A multi-layer printed circuit board structure, a connector module and a memory storage device are provided. The multi-layer printed circuit board structure includes a first layout layer and a second layout layer. The first layout layer includes a shielding element and at least one pad. The shielding element provides the grounding voltage. The second layout layer is disposed corresponding to the first layout layer and includes at least one wire, and one end of each wire is coupled to one of the pads. A predefined proportion of the wire is covered by a projection plane of the shielding element projected on the second layout layer.

Abstract translation: 提供多层印刷电路板结构，连接器模块和存储器存储装置。 多层印刷电路板结构包括第一布局层和第二布局层。 第一布局层包括屏蔽元件和至少一个焊盘。 屏蔽元件提供接地电压。 第二布局层被布置成对应于第一布局层并且包括至少一根导线，并且每根导线的一端耦合到其中一个焊盘。 线的预定比例被投影在第二布局层上的屏蔽元件的投影平面所覆盖。

公开(公告)号：US20130159641A1

公开(公告)日：2013-06-20

申请号：US13772363

申请日：2013-02-21

Applicant: Phison Electronics Corp.

Inventor： Hsiang-Hsiung Yu ,  Ta-Chuan Wei ,  Yun-Chieh Chen ,  Yu-Chung Shen

IPC: G06F12/00

CPC classification number: G06F12/00 ,  G06F3/0614 ,  G06F3/0656 ,  G06F3/0658 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/7203 ,  G06F2212/7207 ,  G11C5/143 ,  G11C16/10 ,  G11C16/30 ,  Y02D10/13

Abstract: A non-volatile memory storage apparatus having a connector, an energy storage circuit, a power regulator and supply circuit, a non-volatile memory module, a memory controller and a buffer memory is provided. The power regulator and supply circuit is configured for transforming an output voltage from the energy storage circuit into a first voltage used for the non-volatile memory module and a second voltage used for the memory controller and the buffer memory. The memory controller is configured for writing data stored temporarily in the buffer memory into the non-volatile memory module with a special writing mode when receiving a detecting signal indicating that an input voltage is continuously smaller than a predetermined voltage for a predetermined period or receiving a detecting signal indicating that an inactive status of the connector or receiving a suspend mode signal, a warm reset signal or a hot reset signal from a host system.

Abstract translation: 提供一种具有连接器，能量存储电路，功率调节器和电源电路，非易失性存储器模块，存储器控制器和缓冲存储器的非易失性存储器存储装置。 功率调节器和电源电路被配置为将来自能量存储电路的输出电压变换为用于非易失性存储器模块的第一电压和用于存储器控制器和缓冲存储器的第二电压。 存储器控制器被配置为当接收到指示输入电压连续小于预定电压达预定时间段的检测信号或者接收到一个或多个存储器时，将临时存储在缓冲存储器中的数据以特殊写入模式写入非易失性存储器模块 检测信号，指示连接器的不活动状态或接收来自主机系统的挂起模式信号，热复位信号或热复位信号。

公开(公告)号：US20160018997A1

公开(公告)日：2016-01-21

申请号：US14480643

申请日：2014-09-09

Applicant: PHISON ELECTRONICS CORP.

Inventor： Hsiang-Hsiung Yu ,  Yuan-Cheng Chang ,  Wei-Cheng Wu

IPC: G06F3/06

CPC classification number: G06F13/1673

Abstract: A memory storage device including a first and a second connection interface units, a memory control circuit unit and an interfacing circuit is provided. The first connection interface unit and the second connection interface unit are electrically connected to an input/output channel of the memory control circuit unit. The interfacing circuit is disposed between the memory control circuit unit and at least one of the first and the second connection interface units. The interfacing circuit is configured to provide determination information of an electrically connecting configuration between at least one host system and the at least one of the first and the second connection interface units. The memory control circuit unit is configured to provide different operation functions to the at least one host system based on the determination information.

Abstract translation: 提供了包括第一和第二连接接口单元，存储器控制电路单元和接口电路的存储器存储设备。 第一连接接口单元和第二连接接口单元电连接到存储器控制电路单元的输入/输出通道。 接口电路设置在存储器控制电路单元和第一和第二连接接口单元中的至少一个之间。 接口电路被配置为提供至少一个主机系统与第一和第二连接接口单元中的至少一个之间的电连接配置的确定信息。 存储器控制电路单元被配置为基于确定信息向至少一个主机系统提供不同的操作功能。

公开(公告)号：US20150305143A1

公开(公告)日：2015-10-22

申请号：US14297646

申请日：2014-06-06

Applicant: PHISON ELECTRONICS CORP.

Inventor： Yun-Chieh Chen ,  Shih-Kung Lin ,  Ta-Chuan Wei ,  Hsiang-Hsiung Yu

IPC: H05K1/02 ,  H01R13/6581 ,  H01R13/66 ,  G11C5/02 ,  H05K1/11

CPC classification number: H05K1/0219 ,  H01L23/14 ,  H01L23/5225 ,  H01L2924/0002 ,  H01R13/6594 ,  H01R13/6658 ,  H01R24/62 ,  H05K1/0224 ,  H05K1/0225 ,  H05K1/0227 ,  H05K3/46 ,  H05K2201/0723 ,  H01L2924/00

Abstract: A multi-layer printed circuit board structure, a connector module and a memory storage device are provided. The multi-layer printed circuit board structure includes a first layout layer and a second layout layer. The first layout layer includes a shielding element and at least one pad. The shielding element provides the grounding voltage. The second layout layer is disposed corresponding to the first layout layer and includes at least one wire, and one end of each wire is coupled to one of the pads. A predefined proportion of the wire is covered by a projection plane of the shielding element projected on the second layout layer.

Abstract translation: 提供多层印刷电路板结构，连接器模块和存储器存储装置。 多层印刷电路板结构包括第一布局层和第二布局层。 第一布局层包括屏蔽元件和至少一个焊盘。 屏蔽元件提供接地电压。 第二布局层被布置成对应于第一布局层并且包括至少一根导线，并且每根导线的一端耦合到其中一个焊盘。 线的预定比例被投影在第二布局层上的屏蔽元件的投影平面所覆盖。

公开(公告)号：US20140297936A1

公开(公告)日：2014-10-02

申请号：US14306240

申请日：2014-06-17

Applicant: PHISON ELECTRONICS CORP.

Inventor： Hsiang-Hsiung Yu ,  Ta-Chuan Wei ,  Yun-Chieh Chen ,  Yu-Chung Shen

IPC: G06F12/02

CPC classification number: G06F12/00 ,  G06F3/0614 ,  G06F3/0656 ,  G06F3/0658 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/7203 ,  G06F2212/7207 ,  G11C5/143 ,  G11C16/10 ,  G11C16/30 ,  Y02D10/13

Abstract: A non-volatile memory storage apparatus having a connector, an energy storage circuit, a power regulator and supply circuit, a non-volatile memory module, a memory controller and a buffer memory is provided. The power regulator and supply circuit is configured for transforming an output voltage from the energy storage circuit into a first voltage used for the non-volatile memory module and a second voltage used for the memory controller and the buffer memory. The memory controller is configured for writing data stored temporarily in the buffer memory into the non-volatile memory module with a special writing mode when receiving a detecting signal indicating that an input voltage is continuously smaller than a predetermined voltage for a predetermined period or receiving a detecting signal indicating that an inactive status of the connector or receiving a suspend mode signal, a warm reset signal or a hot reset signal from a host system.

Abstract translation: 提供一种具有连接器，能量存储电路，功率调节器和电源电路，非易失性存储器模块，存储器控制器和缓冲存储器的非易失性存储器存储装置。 功率调节器和电源电路被配置为将来自能量存储电路的输出电压变换为用于非易失性存储器模块的第一电压和用于存储器控制器和缓冲存储器的第二电压。 存储器控制器被配置为当接收到指示输入电压连续小于预定电压达预定时间段的检测信号或者接收到一个或多个存储器时，将临时存储在缓冲存储器中的数据以特殊写入模式写入非易失性存储器模块 检测信号，指示连接器的不活动状态或接收来自主机系统的挂起模式信号，热复位信号或热复位信号。

公开(公告)号：US09317418B2

公开(公告)日：2016-04-19

申请号：US14306240

申请日：2014-06-17

Applicant: PHISON ELECTRONICS CORP.

Inventor： Hsiang-Hsiung Yu ,  Ta-Chuan Wei ,  Yun-Chieh Chen ,  Yu-Chung Shen

IPC: G11C14/00 ,  G06F12/00 ,  G06F12/02 ,  G11C5/14 ,  G11C16/10 ,  G11C16/30 ,  G06F3/06

CPC classification number: G06F12/00 ,  G06F3/0614 ,  G06F3/0656 ,  G06F3/0658 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/7203 ,  G06F2212/7207 ,  G11C5/143 ,  G11C16/10 ,  G11C16/30 ,  Y02D10/13

Abstract: A non-volatile memory storage apparatus having a connector, an energy storage circuit, a power regulator and supply circuit, a non-volatile memory module, a memory controller and a buffer memory is provided. The power regulator and supply circuit is configured for transforming an output voltage from the energy storage circuit into a first voltage used for the non-volatile memory module and a second voltage used for the memory controller and the buffer memory. The memory controller is configured for writing data stored temporarily in the buffer memory into the non-volatile memory module with a special writing mode when receiving a detecting signal indicating that an input voltage is continuously smaller than a predetermined voltage for a predetermined period or receiving a detecting signal indicating that an inactive status of the connector or receiving a suspend mode signal, a warm reset signal or a hot reset signal from a host system.

公开(公告)号：US09310869B2

公开(公告)日：2016-04-12

申请号：US14462569

申请日：2014-08-19

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chih-Jen Hsu ,  Hsiang-Hsiung Yu ,  Ta-Chuan Wei ,  Yun-Chieh Chen

IPC: G11C16/30 ,  G06F1/26 ,  G06F13/42

CPC classification number: G06F1/266 ,  G06F1/20 ,  G06F1/26 ,  G06F13/4221 ,  G11C16/30

Abstract: A memory storage device, a memory control circuit unit and a power supply method are provided. The power supply method includes: providing a first power voltage to a host interface circuit of the memory storage device; providing a second power voltage to a memory management circuit of the memory storage device; providing a third power voltage to a memory interface circuit of the memory storage device, wherein a reference voltage terminal of the memory interface circuit is coupled to a power input terminal of the memory management circuit. Thus, the overheat problem of the memory storage device due to the voltage conversion may be improved.

Abstract translation: 提供存储器存储装置，存储器控制电路单元和电源方法。 电源方法包括：向存储器存储装置的主机接口电路提供第一电源电压; 向所述存储器存储设备的存储器管理电路提供第二电源电压; 向所述存储器存储装置的存储器接口电路提供第三电源电压，其中所述存储器接口电路的参考电压端子耦合到所述存储器管理电路的电源输入端子。 因此，可以提高由于电压转换引起的存储器存储装置的过热问题。

公开(公告)号：US20150323969A1

公开(公告)日：2015-11-12

申请号：US14462569

申请日：2014-08-19

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chih-Jen Hsu ,  Hsiang-Hsiung Yu ,  Ta-Chuan Wei ,  Yun-Chieh Chen

IPC: G06F1/26 ,  G06F13/42

CPC classification number: G06F1/266 ,  G06F1/20 ,  G06F1/26 ,  G06F13/4221 ,  G11C16/30

Abstract: A memory storage device, a memory control circuit unit and a power supply method are provided. The power supply method includes: providing a first power voltage to a host interface circuit of the memory storage device; providing a second power voltage to a memory management circuit of the memory storage device; providing a third power voltage to a memory interface circuit of the memory storage device, wherein a reference voltage terminal of the memory interface circuit is coupled to a power input terminal of the memory management circuit. Thus, the overheat problem of the memory storage device due to the voltage conversion may be improved.

Abstract translation: 提供存储器存储装置，存储器控制电路单元和电源方法。 电源方法包括：向存储器存储装置的主机接口电路提供第一电源电压; 向所述存储器存储设备的存储器管理电路提供第二电源电压; 向所述存储器存储装置的存储器接口电路提供第三电源电压，其中所述存储器接口电路的参考电压端子耦合到所述存储器管理电路的电源输入端子。 因此，可以提高由于电压转换引起的存储器存储装置的过热问题。