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公开(公告)号：US20200067513A1
公开(公告)日：2020-02-27
申请号：US16465515
申请日：2016-12-30
Applicant: Intel IP Corporation
Inventor： YAIR DGANI , Michael Kerner , Elan Banin , Nati Dinur , Gil Horovitz , Rotem Banin
Abstract: Aspects of a digital phase-lock loop (DPLL) with an adjustable delay between an output clock and a reference clock in accordance with phase noise compensation are generally described herein. An apparatus may include processing circuitry configured to, in a first mode, identify a delay element of a plurality of delay elements based on an associated delay value, and set an initial phase difference value to a phase difference value associated with the identified delay element. The processor circuitry may be further configured to, in a second mode, in a second mode, initialize the DPLL using the initial phase difference value, determine a phase error between a reference clock and a feedback clock based on the initial phase difference value, adjust an output clock signal based on the phase error.
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公开(公告)号：US09912357B1
公开(公告)日：2018-03-06
申请号：US15382808
申请日：2016-12-19
Applicant: Intel IP Corporation
Inventor： Uri Parker , Elan Banin , Michael Kerner , Ofir Degani
CPC classification number: H04B1/02 , G11B20/10055 , G11B20/1024 , H02M1/12 , H02P27/08 , H04B1/04 , H04L27/361
Abstract: A digital polar transmitter arrangement having a digital front end (DFE) and a transmit chain is disclosed. The DFE is configured to resample a baseband signal relative to a carrier frequency at a carrier frequency related sample rate, calculate zero crossing positions of the resampled signal, generate delay to time converter (DTC) commands based on the zero crossing positions, calculate amplitude values for the zero crossing positions and generate dynamic phase alignment (DPA) commands based on the amplitude values. The transmit chain is configured to generate an output signal having amplitude and phase modulation based on the DTC and DPA commands.
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公开(公告)号：US09780945B1
公开(公告)日：2017-10-03
申请号：US15088388
申请日：2016-04-01
Applicant: Intel IP Corporation
Inventor： Rotem Avivi , Michael Kerner
CPC classification number: H04L7/0331 , H03L7/093 , H03L2207/50 , H04B15/02
Abstract: Embodiments related to systems, methods, and computer-readable media to enable a digital phase locked loop are described. In one embodiment, a digital synthesizer comprises a digital phase locked loop with detection circuitry to calculate an estimate of a magnitude and a phase of a spurious response from an error signal within the digital phase locked loop. The digital phase locked loop further comprises generation circuitry to generate an inverse spur based on the estimate of the magnitude and the phase, and further comprises injection circuitry to inject the inverse spur into the digital phase locked loop. In some embodiments, least mean squares (LMS), recursive least squares (RLS), or other such adaptation is used to estimate the magnitude and phase of the spurious response.
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公开(公告)号：US10075201B1
公开(公告)日：2018-09-11
申请号：US15648205
申请日：2017-07-12
Applicant: Intel IP Corporation
Inventor： Avi Gazneli , Michael Kerner , Itay Almog , Amit Knoll
CPC classification number: H04B1/0475 , H03F1/3247 , H03F1/3258 , H03F3/195 , H03F3/245 , H03F2200/294 , H03F2200/321 , H03F2200/451 , H04B2001/0425
Abstract: An adaptive controller for a nonlinear system includes a Volterra filter having a transfer function defined by P coefficients. The controller includes an alignment/compensation circuit, which aligns the input samples to the output samples of the nonlinear system. The controller generates a P×P matrix using at least one of input samples to, or output samples from the nonlinear system and normalizes each element of the P×P matrix using a respective normalization factor. The controller generates and solves a system of P linear equations from the P×P matrix and a P×1 matrix derived from input and output samples of the nonlinear system using Cholesky decomposition that may include Fast Inverse Square Root operations and forward backward elimination to generate P values. The controller multiplies each of the P values by an inverse of a respective one of the normalization factors to generate the P coefficients for the Volterra filter.
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公开(公告)号：US20180254852A1
公开(公告)日：2018-09-06
申请号：US15449078
申请日：2017-03-03
Applicant: Intel IP Corporation
Inventor： Rotem Avivi , Michael Kerner , Assaf Gurevitz
CPC classification number: H04L1/0033 , H04B1/0475 , H04B1/40 , H04B1/525 , H04B7/0404 , H04L1/0036 , H04L27/0002
Abstract: A spur cancelation system includes error circuitry, inverse spur circuitry, and injection circuitry. The error circuitry is configured to generate an error signal based at least on a first transceiver signal in a transceiver signal processing chain. The inverse spur circuitry is configured to, based at least on the error signal, determine a gain and a phase of a spur signal in the transceiver signal and generate an inverse spur signal based at least on the gain and the phase of the spur signal. The injection circuitry is configured to inject the inverse spur signal to cancel a spur in a second transceiver signal in the transceiver signal processing chain.
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Patent Agency Ranking
公开(公告)号：US10027356B2
公开(公告)日：2018-07-17
申请号：US15274509
申请日：2016-09-23
Applicant: Intel IP Corporation
Inventor： Elan Banin , Uri Parker , Ofir Degani , Michael Kerner
Abstract: Devices and methods of compensating for a bandpass filter are generally described. A DTx includes a BPF from which an output signal is produced and a DFE having a zero crossing (ZC) pre-distorter (ZCPD). The ZCPD compensates for ZC distortion from a desired analog signal caused by the BPF. The ZCPD adjusts a DTC code word to generate a DTx output signal to be applied to the BPF. The compensation is dependent on a magnitude of the square wave immediately prior to and after the ZC. The compensated DTC and a DPA code word are used to generate the DTx output signal. The compensation produced by the ZCPD is free from compensation for non-linear responses to the DTC and DPA code words.
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公开(公告)号：US09991913B1
公开(公告)日：2018-06-05
申请号：US15371768
申请日：2016-12-07
Applicant: Intel IP Corporation
Inventor： Nati Dinur , Uri Perlmutter , Michael Kerner
CPC classification number: H04B1/0475 , H03F1/025 , H03F1/3241 , H03F3/189 , H04B2001/0408 , H04L27/2626 , H04L27/32
Abstract: An envelope tracking arrangement is disclosed and includes a level select component, a chunk supply component and a power amplifier. The level select component is configured to segment an input signal into chunks based on time and to select a chunk level for each chunk based on information or envelope information. The chunk supply component is configured to selectively provide a discrete supply voltage according to the selected chunk level. The power amplifier is configured to generate a radio frequency (RF) output signal based on the input signal and utilizing the discrete supply voltage.
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公开(公告)号：US10768580B2
公开(公告)日：2020-09-08
申请号：US16474562
申请日：2017-03-02
Applicant: Intel IP Corporation
Inventor： Yair Dgani , Michael Kerner , Elan Banin , Evgeny Shumaker , Gil Horovitz , Ofir Degani , Rotem Banin , Aryeh Farber , Rotem Avivi , Eshel Gordon , Tami Sela
Abstract: A time-to-digital converter is provided. The time-to-digital converter includes a delay circuit configured to iteratively delay a reference signal for generating a plurality of delayed reference signals. Further, the time-to-digital converter includes a plurality of sample circuits each configured to sample an oscillation signal based on one of the plurality of delayed reference signals. The time-to-digital converter additionally includes a control circuit configured to de-activate at least one of the plurality of sample circuits based on a predicted value of the phase of the oscillation signal.
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公开(公告)号：US20190384230A1
公开(公告)日：2019-12-19
申请号：US16474562
申请日：2017-03-02
Applicant: Intel IP Corporation
Inventor： Yair Dgani , Michael Kerner , Elan Banin , Evgeny Shumaker , Gil Horovitz , Ofir Degani , Rotem Banin , Aryeh Farber , Rotem Avivi , Eshel Gordon , Tami Sela
Abstract: A time-to-digital converter is provided. The time-to-digital converter includes a delay circuit configured to iteratively delay a reference signal for generating a plurality of delayed reference signals. Further, the time-to-digital converter includes a plurality of sample circuits each configured to sample an oscillation signal based on one of the plurality of delayed reference signals. The time-to-digital converter additionally includes a control circuit configured to de-activate at least one of the plurality of sample circuits based on a predicted value of the phase of the oscillation signal.
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公开(公告)号：US10177719B2
公开(公告)日：2019-01-08
申请号：US15584076
申请日：2017-05-02
Applicant: Intel IP Corporation
Inventor： Avi Gazneli , Michael Kerner , Amir Rubin , Itay Almog , Avi Sulimarski
Abstract: A method for predistorting an input signal of an amplifier device comprises evaluating a selection criterion for a computational model of the amplifier device. The computational model provides an output signal of the amplifier device for the input signal of the amplifier device. Further, the method comprises selecting between a first computational model of the amplifier device and a second computational model of the amplifier device based on the evaluated selection criterion. Additionally, the method comprises predistorting the input signal of the amplifier device using the selected computational model.
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