公开(公告)号：US10915461B2

公开(公告)日：2021-02-09

申请号：US16292762

申请日：2019-03-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ekaterina M. Ambroladze ,  Robert J. Sonnelitter, III ,  Matthias Klein ,  Craig Walters ,  Kevin Lopes ,  Michael A. Blake ,  Tim Bronson ,  Kenneth Klapproth ,  Vesselina Papazova ,  Hieu T Huynh

IPC: G06F12/126 ,  G06F12/084 ,  G06F12/0811

Abstract: Embodiments of the present invention are directed to a computer-implemented method for cache eviction. The method includes detecting a first data in a shared cache and a first cache in response to a request by a first processor. The first data is determined to have a mid-level cache eviction priority. A request is detected from a second processor for a same first data as requested by the first processor. However, in this instance, the second processor has indicated that the same first data has a low-level cache eviction priority. The first data is duplicated and loaded to a second cache, however, the data has a low-level cache eviction priority at the second cache.

公开(公告)号：US20200301831A1

公开(公告)日：2020-09-24

申请号：US16360254

申请日：2019-03-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Chad G. Wilson ,  Robert J Sonnelitter, III ,  Tim Bronson ,  Ekaterina M. Ambroladze ,  Hieu T Huynh ,  Jason D Kohl ,  Chakrapani Rayadurgam

IPC: G06F12/084

Abstract: Methods and systems for cache management are provided. Aspects include providing a drawer including a plurality of clusters, each of the plurality of clusters including a plurality of processor each having one or more cores, wherein each of the one or more cores shares a first cache memory, providing a second cache memory shared among the plurality of clusters, and receiving a cache line request from one of the one or more cores to the first cache memory, wherein the first cache memory sends a request to a memory controller to retrieve the cache line from a memory, store the cache line in the first cache memory, create a directory state associated with the cache line, and provide the directory state to the second cache memory to create a directory entry for the cache line.

公开(公告)号：US11221794B2

公开(公告)日：2022-01-11

申请号：US16280577

申请日：2019-02-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Tim Bronson ,  Hieu T. Huynh ,  Kenneth Klapproth

IPC: G06F3/06 ,  G06F12/0895

Abstract: Methods, systems and computer program products for providing access to a spare memory array element (“MAE”) are provided. Aspects include storing a row number a column number associated with a defective MAE of a plurality of MAEs. The plurality of MAEs are logically arranged in a plurality of rows and a plurality of columns. Aspects also include receiving a command to access a cache line. The cache line corresponds to a selected row of MAEs of the plurality of MAEs. Responsive to determining that the selected row matches the row number that is associated with the defective MAE, aspects include activating one or more column shifters to prevent access to the defective MAE and provide access to a spare MAE when accessing the cache line. The activation of the one of more column shifters is based on the column number that is associated with the defective MAE.

公开(公告)号：US20200264797A1

公开(公告)日：2020-08-20

申请号：US16280641

申请日：2019-02-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jason D. Kohl ,  Tim Bronson ,  Hieu T. Huynh ,  Michael Andrew Blake

IPC: G06F3/06

Abstract: Methods, systems and computer program products for evacuating memory from a drawer in a live multi-node system are provided. Aspects include placing a first drawer into an evacuation mode. The evacuation mode includes a cessation of non-evacuation operations and provides for a transfer of data stored by memory of the first drawer to a destination drawer using dynamic memory reallocation (DMR). Aspects also include transmitting a store request by the first drawer to the destination drawer. The store request represents a request to transfer the data stored by the memory of the first drawer to the destination drawer for storage by the destination drawer. Aspects also include transmitting the data stored by the memory of the first drawer to the destination drawer. The data is transmitted by the first drawer using a local pool of fetch/store controllers.

公开(公告)号：US10831661B2

公开(公告)日：2020-11-10

申请号：US16380307

申请日：2019-04-10

Applicant: International Business Machines Corporation

Inventor： Ekaterina M. Ambroladze ,  Tim Bronson ,  Robert J. Sonnelitter, III ,  Deanna P. D. Berger ,  Chad G. Wilson ,  Kenneth Douglas Klapproth ,  Arthur O'Neill ,  Michael A. Blake ,  Guy G. Tracy

IPC: G06F12/0815

Abstract: Processing simultaneous data requests regardless of active request in the same addressable index of a cache. In response to the cache miss in the given congruence, if the number of other compartments in the given congruence class that have an active operation is less than a predetermined threshold, setting a Do Not Cast Out (DNCO) pending indication for each of the compartments that have an active operation in order to block access to each of the other compartments that have active operations and, if the number of other compartments in the given congruence class that have an active operation is not less than a predetermined threshold, blocking another cache miss from occurring in the compartments of the given congruence class by setting a congruence class block pending indication for the given congruence class in order to block access to each of the other compartments of the given congruence class.

公开(公告)号：US20200264803A1

公开(公告)日：2020-08-20

申请号：US16280577

申请日：2019-02-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Tim Bronson ,  Hieu T. Huynh ,  Kenneth Klapproth

IPC: G06F3/06 ,  G06F12/0895

Abstract: Methods, systems and computer program products for providing access to a spare memory array element (“MAE”) are provided. Aspects include storing a row number a column number associated with a defective MAE of a plurality of MAEs. The plurality of MAEs are logically arranged in a plurality of rows and a plurality of columns. Aspects also include receiving a command to access a cache line. The cache line corresponds to a selected row of MAEs of the plurality of MAEs. Responsive to determining that the selected row matches the row number that is associated with the defective MAE, aspects include activating one or more column shifters to prevent access to the defective MAE and provide access to a spare MAE when accessing the cache line. The activation of the one of more column shifters is based on the column number that is associated with the defective MAE.

公开(公告)号：US20200327058A1

公开(公告)日：2020-10-15

申请号：US16380307

申请日：2019-04-10

Applicant: International Business Machines Corporation

Inventor： Ekaterina M. Ambroladze ,  Tim Bronson ,  Robert J. Sonnelitter, III ,  Deanna P. D. Berger ,  Chad G. Wilson ,  Kenneth Douglas Klapproth ,  Arthur O'Neill ,  Michael A. Blake ,  Guy G. Tracy

IPC: G06F12/0815

Abstract: Processing simultaneous data requests regardless of active request in the same addressable index of a cache. In response to the cache miss in the given congruence, if the number of other compartments in the given congruence class that have an active operation is less than a predetermined threshold, setting a Do Not Cast Out (DNCO) pending indication for each of the compartments that have an active operation in order to block access to each of the other compartments that have active operations and, if the number of other compartments in the given congruence class that have an active operation is not less than a predetermined threshold, blocking another cache miss from occurring in the compartments of the given congruence class by setting a congruence class block pending indication for the given congruence class in order to block access to each of the other compartments of the given congruence class.

公开(公告)号：US20200264977A1

公开(公告)日：2020-08-20

申请号：US16275436

申请日：2019-02-14

Applicant: International Business Machines Corporation

Inventor： Arun Iyengar ,  Tim Bronson ,  Michael Andrew Blake ,  Vesselina Papazova ,  Arthur O'Neill ,  Jason D. Kohl1 ,  Kenneth Klapproth

IPC: G06F12/0806 ,  G06F12/0817

Abstract: Provided are systems, methods, and media for simultaneous, non-atomic request processing of snooped operations of a broadcast scope within a SMP system. An example method includes detecting, by a first controller, based on a set of coherency resolution conditions, whether there are coherency resolution problems between two snooped operations. The method includes in response to detecting, by the first controller, that coherency resolution problems will not result, transmitting, from the first controller to a second controller, an indication signal indicating that coherency resolution problems will not result from the operation. The set of coherency resolution conditions includes: (a) detecting that a second operation of the two snooped operations operation is of a predetermined type, (b) detecting at time of snooping of the second operation that a directory state does not allow for exclusive data, and (c) detecting that the first controller has started committing to an update.

公开(公告)号：US11048427B2

公开(公告)日：2021-06-29

申请号：US16280641

申请日：2019-02-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jason D. Kohl ,  Tim Bronson ,  Hieu T. Huynh ,  Michael Andrew Blake

IPC: G06F12/00 ,  G06F3/06

Abstract: Methods, systems and computer program products for evacuating memory from a drawer in a live multi-node system are provided. Aspects include placing a first drawer into an evacuation mode. The evacuation mode includes a cessation of non-evacuation operations and provides for a transfer of data stored by memory of the first drawer to a destination drawer using dynamic memory reallocation (DMR). Aspects also include transmitting a store request by the first drawer to the destination drawer. The store request represents a request to transfer the data stored by the memory of the first drawer to the destination drawer for storage by the destination drawer. Aspects also include transmitting the data stored by the memory of the first drawer to the destination drawer. The data is transmitted by the first drawer using a local pool of fetch/store controllers.

公开(公告)号：US10901902B2

公开(公告)日：2021-01-26

申请号：US16360254

申请日：2019-03-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Chad G. Wilson ,  Robert J Sonnelitter, III ,  Tim Bronson ,  Ekaterina M. Ambroladze ,  Hieu T Huynh ,  Jason D Kohl ,  Chakrapani Rayadurgam

IPC: G06F12/10 ,  G06F12/084

Abstract: Methods and systems for cache management are provided. Aspects include providing a drawer including a plurality of clusters, each of the plurality of clusters including a plurality of processor each having one or more cores, wherein each of the one or more cores shares a first cache memory, providing a second cache memory shared among the plurality of clusters, and receiving a cache line request from one of the one or more cores to the first cache memory, wherein the first cache memory sends a request to a memory controller to retrieve the cache line from a memory, store the cache line in the first cache memory, create a directory state associated with the cache line, and provide the directory state to the second cache memory to create a directory entry for the cache line.