公开(公告)号：US20200152698A1

公开(公告)日：2020-05-14

申请号：US16184518

申请日：2018-11-08

Applicant: Headway Technologies, Inc.

Inventor： Huanlong Liu ,  Guenole Jan ,  Ru-Ying Tong ,  Jian Zhu ,  Yuan-Jen Lee ,  Jodi Mari Iwata ,  Sahil Patel ,  Vignesh Sundar

IPC: H01L27/22 ,  H01L43/12

Abstract: A fabrication process for an STT MTJ MRAM device includes steps of cooling the device at individual or at multiple stages in its fabrication. The cooling process, which may be equally well applied during the fabrication of other multi-layered devices, is demonstrated to produce an operational device that is more resistant to adverse thermal effects during operation that would normally cause a similar device not so fabricated to lose stored data and otherwise fail to operate properly.

公开(公告)号：US20190140168A1

公开(公告)日：2019-05-09

申请号：US16221868

申请日：2018-12-17

Applicant: Headway Technologies, Inc.

Inventor： Jian Zhu ,  Guenole Jan ,  Yuan-Jen Lee ,  Huanlong Liu ,  Ru-Ying Tong ,  Jodi Mari Iwata ,  Vignesh Sundar ,  Luc Thomas ,  Yu-Jen Wang ,  Sahil Patel

IPC: H01L43/12 ,  H01L43/10 ,  H01L43/08 ,  H01F10/16 ,  H01F10/32 ,  H01F10/30 ,  G11C11/16 ,  H01F41/30

Abstract: A seed layer stack with a uniform top surface having a peak to peak roughness of 0.5 nm is formed by sputter depositing an amorphous layer on a smoothing layer such as Mg where the latter has a resputtering rate 2 to 30× that of the amorphous layer. The uppermost seed (template) layer is NiW, NiMo, or one or more of NiCr, NiFeCr, and Hf while the bottommost seed layer is one or more of Ta, TaN, Zr, ZrN, Nb, NbN, Mo, MoN, TiN, W, WN, and Ru. Accordingly, perpendicular magnetic anisotropy in an overlying magnetic layer is substantially maintained during high temperature processing up to 400° C. and is advantageous for magnetic tunnel junctions in embedded MRAMs, spintronic devices, or in read head sensors. The amorphous seed layer is SiN, TaN, or CoFeM where M is B or another element with a content that makes CoFeM amorphous as deposited.

公开(公告)号：US20180294405A1

公开(公告)日：2018-10-11

申请号：US15479514

申请日：2017-04-05

Applicant: Headway Technologies, Inc.

Inventor： Yu-Jen Wang ,  Dongna Shen ,  Vignesh Sundar ,  Sahil Patel

IPC: H01L43/12 ,  H01L43/02 ,  H01L43/08

CPC classification number: H01L43/12

Abstract: A method for etching a magnetic tunneling junction (MTJ) structure is described. A stack of MTJ layers is provided on a bottom electrode. A top electrode is provided on the MTJ stack. The top electrode is patterned. Thereafter, the MTJ stack not covered by the patterned top electrode is oxidized or nitridized. Then, the MTJ stack is patterned to form a MTJ device wherein any sidewall re-deposition formed on sidewalls of the MTJ device is non-conductive and wherein some of the dielectric layer remains on horizontal surfaces of the bottom electrode.

公开(公告)号：US09935261B1

公开(公告)日：2018-04-03

申请号：US15479522

申请日：2017-04-05

Applicant: Headway Technologies, Inc.

Inventor： Sahil Patel ,  Ru-Ying Tong ,  Dongna Shen ,  Yu-Jen Wang ,  Vignesh Sundar

IPC: G11B5/33 ,  H01L43/08 ,  H01L43/12 ,  H01L43/02 ,  H01L27/22

CPC classification number: H01L43/08 ,  H01L27/222 ,  H01L43/02 ,  H01L43/12

Abstract: A magnetic device for magnetic random access memory (MRAM), spin torque MRAM, or spin torque oscillator technology is disclosed wherein a perpendicularly magnetized magnetic tunnel junction (p-MTJ) with a sidewall is formed between a bottom electrode and a top electrode. A first dielectric layer is 3 to 400 Angstroms thick, and formed on the p-MTJ sidewall with a physical vapor deposition RF sputtering process to establish a thermally stable interface with the p-MTJ up to temperatures around 400° C. during CMOS fabrication. The first dielectric layer may comprise one or more of B, Ge, and alloys thereof, and an oxide, nitride, carbide, oxynitride, or carbonitride. The second dielectric layer is up to 2000 Angstroms thick and may be one or more of SiOYNZ, AlOYNZ, TiOYNZ, SiCYNZ, or MgO where y+z>0.

公开(公告)号：US20230217834A1

公开(公告)日：2023-07-06

申请号：US18119959

申请日：2023-03-10

Applicant: Headway Technologies, Inc.

Inventor： Vignesh Sundar ,  Yi Yang ,  Dongna Shen ,  Zhongjian Teng ,  Jesmin Haq ,  Sahil Patel ,  Yu-Jen Wang ,  Tom Zhong

IPC: H10N50/01 ,  H10N50/10

CPC classification number: H10N50/01 ,  H10N50/10

Abstract: A plurality of conductive via connections are fabricated on a substrate located at positions where MTJ devices are to be fabricated, wherein a width of each of the conductive via connections is smaller than or equivalent to a width of the MTJ devices. The conductive via connections are surrounded with a dielectric layer having a height sufficient to ensure that at the end of a main MTJ etch, an etch front remains in the dielectric layer surrounding the conductive via connections. Thereafter, a MTJ film stack is deposited on the plurality of conductive via connections surrounded by the dielectric layer. The MTJ film stack is etched using an ion beam etch process (IBE), etching through the MTJ film stack and into the dielectric layer surrounding the conductive via connections to form the MTJ devices wherein by etching into the dielectric layer, re-deposition on sidewalls of the MTJ devices is insulating.

公开(公告)号：US11289645B2

公开(公告)日：2022-03-29

申请号：US16236705

申请日：2018-12-31

Applicant: Headway Technologies, Inc.

Inventor： Yi Yang ,  Vignesh Sundar ,  Dongna Shen ,  Sahil Patel ,  Ru-Ying Tong ,  Yu-Jen Wang

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/02

Abstract: A complementary metal oxide semiconductor (CMOS) device comprises a first metal line, a first metal via on the first metal line, a magnetic tunneling junction (MTJ) device on the first metal via wherein the first metal via acts as a bottom electrode for the MTJ device, a second metal via on the MTJ device, and a second metal line on the second metal via.

公开(公告)号：US10784310B2

公开(公告)日：2020-09-22

申请号：US16184518

申请日：2018-11-08

Applicant: Headway Technologies, Inc.

Inventor： Huanlong Liu ,  Guenole Jan ,  Ru-Ying Tong ,  Jian Zhu ,  Yuan-Jen Lee ,  Jodi Mari Iwata ,  Sahil Patel ,  Vignesh Sundar

IPC: H01L27/22 ,  H01L43/12 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: A fabrication process for an STT MTJ MRAM device includes steps of cooling the device at individual or at multiple stages in its fabrication. The cooling process, which may be equally well applied during the fabrication of other multi-layered devices, is demonstrated to produce an operational device that is more resistant to adverse thermal effects during operation that would normally cause a similar device not so fabricated to lose stored data and otherwise fail to operate properly.

公开(公告)号：US20190088866A1

公开(公告)日：2019-03-21

申请号：US16173201

申请日：2018-10-29

Applicant: Headway Technologies, Inc.

Inventor： Jian Zhu ,  Guenole Jan ,  Yuan-Jen Lee ,  Huanlong Liu ,  Ru-Ying Tong ,  Jodi Mari Iwata ,  Vignesh Sundar ,  Luc Thomas ,  Yu-Jen Wang ,  Sahil Patel

IPC: H01L43/12 ,  H01F10/30 ,  H01F41/30 ,  H01F10/32 ,  H01L43/10 ,  H01F10/16 ,  H01L43/08 ,  G11C11/16

Abstract: A seed layer stack with a uniform top surface having a peak to peak roughness of 0.5 nm is formed by sputter depositing an amorphous layer on a smoothing layer such as Mg where the latter has a resputtering rate 2 to 30× that of the amorphous layer. The seed layer stack may be repeated to give a laminate of two amorphous layers and two smoothing layers, and is advantageous for enhancing performance in magnetic tunnel junctions in embedded MRAMs, spintronic devices, or in read head sensors. A template layer such as NiCr may be formed on the uppermost smoothing layer to promote and maintain perpendicular magnetic anisotropy in an overlying magnetic layer during high temperature processing up to 400° C. The amorphous seed layer is SiN, TaN, or CoFeM where M is B or another element with a content that makes CoFeM amorphous as deposited.

公开(公告)号：US10038138B1

公开(公告)日：2018-07-31

申请号：US15728839

申请日：2017-10-10

Applicant: Headway Technologies, Inc.

Inventor： Sahil Patel ,  Yu-Jen Wang ,  Dongna Shen

IPC: H01L43/12 ,  H01L43/10 ,  H01L43/08 ,  H01L41/47 ,  H01L43/02

CPC classification number: H01L43/12 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: A process flow for forming and encapsulating magnetic tunnel junction (MTJ) nanopillars is disclosed wherein MTJ layers including a reference layer (RL), free layer (FL), and tunnel barrier layer (TB) are first patterned by reactive ion etching or ion beam etching to form MTJ sidewalls. A plurality of MTJs on a substrate is heated (annealed) at a station in a process chamber to substantially crystallize the RL, FL, and TB to a body centered cubic (bcc) structure without recrystallization from the edge of the device before an encapsulation layer is deposited thereby ensuring lattice matching between the RL and TB, and between the FL and TB. The encapsulation layer is deposited at the same station as the anneal step without breaking vacuum, and preferably using a physical vapor deposition to prevent reactive species from attacking MTJ sidewalls. Magnetoresistive ratio is improved especially for MTJs with critical dimensions below 70 nm.

公开(公告)号：US20210135097A1

公开(公告)日：2021-05-06

申请号：US16672981

申请日：2019-11-04

Applicant: Headway Technologies, Inc.

Inventor： Dongna Shen ,  Yi Yang ,  Sahil Patel ,  Vignesh Sundar ,  Yu-Jen Wang

IPC: H01L43/12 ,  H01L43/02

Abstract: A method for fabricating a magnetic tunneling junction (MTJ) structure is described. A MTJ film stack is deposited on a bottom electrode on a substrate. The MTJ film stack is first ion beam etched (IBE) using a first angle and a first energy to form a MTJ device wherein conductive re-deposition forms on sidewalls of the MTJ device. Thereafter, the conductive re-deposition is oxidized. Thereafter, the MTJ device is second ion beam etched (IBE) at a second angle and a second energy to remove oxidized re-deposition.