公开(公告)号：US20210143323A1

公开(公告)日：2021-05-13

申请号：US16681351

申请日：2019-11-12

Applicant: Applied Materials, Inc.

Inventor： Jong Mun KIM ,  Minrui YU ,  Chando PARK ,  Mang-Mang LING ,  Jaesoo AHN ,  Chentsau Chris YING ,  Srinivas D. NEMANI ,  Mahendra PAKALA ,  Ellie Y. YIEH

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/02 ,  H01L43/10

Abstract: Embodiments of the disclosure provide methods and apparatus for fabricating magnetic tunnel junction (MTJ) structures on a substrate for MRAM applications. In one embodiment, a method for forming a magnetic tunnel junction (MTJ) device structure includes performing a patterning process by an ion beam etching process in a processing chamber to pattern a film stack disposed on a substrate, wherein the film stack comprises a reference layer, a tunneling barrier layer and a free layer disposed on the tunneling barrier, and determining an end point for the patterning process.

公开(公告)号：US20200161541A1

公开(公告)日：2020-05-21

申请号：US16195313

申请日：2018-11-19

Applicant: Applied Materials, Inc.

Inventor： Hsin-wei TSENG ,  Chando PARK ,  Jaesoo AHN ,  Lin XUE ,  Mahendra PAKALA

IPC: H01L43/12 ,  H01L27/22

Abstract: Embodiments of the disclosure provide methods and apparatus for fabricating magnetic tunnel junction (MTJ) structures on a substrate in for hybrid (or called integrated) spin-orbit-torque magnetic spin-transfer-torque magnetic random access memory (SOT-STT MRAM) applications. In one embodiment, the method includes one or more magnetic tunnel junction structures disposed on a substrate, the magnetic tunnel junction structure comprising a first ferromagnetic layer and a second ferromagnetic layer sandwiching a tunneling barrier layer, a spin orbit torque (SOT) layer disposed on the magnetic tunnel junction structure, and a back end structure disposed on the spin orbit torque (SOT) layer.

公开(公告)号：US20180277370A1

公开(公告)日：2018-09-27

申请号：US15988830

申请日：2018-05-24

Applicant: Applied Materials, Inc.

Inventor： Thomas Jongwan KWON ,  Rui CHENG ,  Abhijit Basu MALLICK ,  Er-Xuan PING ,  Jaesoo AHN

IPC: H01L21/033 ,  H01L21/3213 ,  H01L21/308 ,  H01L21/02 ,  H01L49/02 ,  H01L21/311 ,  H01L27/11582

CPC classification number: H01L21/0338 ,  H01L21/02109 ,  H01L21/02115 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31144 ,  H01L21/32136 ,  H01L21/32139 ,  H01L27/11582 ,  H01L28/00

Abstract: Implementations of the present disclosure relate to improved hardmask materials and methods for patterning and etching of substrates. A plurality of hardmasks may be utilized in combination with patterning and etching processes to enable advanced device architectures. In one implementation, a first hardmask and a second hardmask disposed on a substrate having various material layers disposed thereon. The second hardmask may be utilized to pattern the first hardmask during a first etching process. A third hardmask may be deposited over the first and second hardmasks and a second etching process may be utilized to form channels in the material layers.

公开(公告)号：US20230389441A1

公开(公告)日：2023-11-30

申请号：US18231414

申请日：2023-08-08

Applicant: Applied Materials, Inc.

Inventor： Minrui YU ,  Wenhui WANG ,  Jaesoo AHN ,  Jong Mun KIM ,  Sahil PATEL ,  Lin XUE ,  Chando PARK ,  Mahendra PAKALA ,  Chentsau Chris YING ,  Huixiong DAI ,  Christopher S. NGAI

IPC: H10N50/10 ,  G01R33/09 ,  G11C11/16 ,  H10B61/00 ,  H10N50/85 ,  H10N52/01 ,  H10N52/80

CPC classification number: H10N50/10 ,  G01R33/098 ,  G11C11/161 ,  G01R33/095 ,  H10B61/00 ,  H10N50/85 ,  H10N52/01 ,  H10N52/80

Abstract: Embodiments of the present disclosure generally include spin-orbit torque magnetoresistive random-access memory (SOT-MRAM) devices and methods of manufacture thereof. The SOT-MRAM devices described herein include an SOT layer laterally aligned with a magnetic tunnel junction (MTJ) stack and formed over a trench in an interconnect. Thus, the presence of the SOT layer outside the area of the MTJ stack is eliminated, and electric current passes from the interconnect to the SOT layer by SOT-interconnect overlap. The devices and methods described herein reduce the formation of shunting current and enable the MTJ to self-align with the SOT layer in a single etching process.

公开(公告)号：US20200251495A1

公开(公告)日：2020-08-06

申请号：US16265192

申请日：2019-02-01

Applicant: Applied Materials, Inc.

Inventor： Jaesoo AHN ,  Thomas KWON ,  Mahendra PAKALA

IPC: H01L27/11597 ,  H01L29/51 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28

Abstract: Embodiments of the present disclosure provide an apparatus and methods for forming stair-like structures with accurate profiles and dimension control for manufacturing three dimensional (3D) stacked memory cell semiconductor devices. In one embodiment, a memory cell device includes a film stack comprising alternating pairs of dielectric layers and conductive structures horizontally formed on a substrate, an opening formed in the film stack, wherein the opening is filled with a channel layer and a center filling layer, and a protective liner layer disposed between the conductive structure and the channel layer.

公开(公告)号：US20200161542A1

公开(公告)日：2020-05-21

申请号：US16290621

申请日：2019-03-01

Applicant: Applied Materials, Inc.

Inventor： Jaesoo AHN ,  Chando PARK ,  Hsin-wei TSENG ,  Lin XUE ,  Mahendra PAKALA

IPC: H01L43/12 ,  H01L43/10 ,  H01L43/02

Abstract: The bottom-pinned spin-orbit torque (SOT) MRAM devices are fabricated to form high quality interfaces between layers including the spin-orbit torque (SOT) layer and the free layer of the magnetic tunnel junction (MTJ) by forming those layers under vacuum, without breaking vacuum in between formation of the layers. An encapsulation layer is used as an etch stop and to protect the free layer. The encapsulation layer is etched back prior to the deposition of a metal layer. The metal layer forms a plurality of metal lines that are electrically connected to two or more sides of the SOT layer and are electrically coupled to the SOT layer to transfer current through the SOT layer. The metal lines are not in contact with a top surface of the SOT layer which has a dielectric layer disposed thereon.

公开(公告)号：US20160351799A1

公开(公告)日：2016-12-01

申请号：US14755964

申请日：2015-06-30

Applicant: Applied Materials, Inc.

Inventor： Lin XUE ,  Mahendra PAKALA ,  Hao CHEN ,  Jaesoo AHN

IPC: H01L43/12 ,  H01L43/08 ,  H01L43/02

CPC classification number: H01L43/12

Abstract: Device structures and methods for fabricating device structures are provided herein. Magnetic random access memory (MRAM) devices described herein may include a film stack comprising a magnetic tunneling junction layer, a dielectric capping layer, an etch stop layer, a conductive hard mask layer, a dielectric hard mask layer, a spin on carbon layer, and an anti-reflective coating layer. The film stack may be etched by one or more selected chemistries to achieve improved film stack sidewall verticality. Memory cells having increasingly uniform and reduced critical dimensions may be fabricated utilizing the methods and devices described herein.

Abstract translation: 本文提供了用于制造器件结构的器件结构和方法。 本文描述的磁性随机存取存储器（MRAM）器件可以包括膜堆叠，其包括磁性隧道结层，介电覆盖层，蚀刻停止层，导电硬掩模层，电介质硬掩模层，自旋碳层， 和抗反射涂层。 可以通过一个或多个选择的化学物质来蚀刻膜堆叠，以实现改进的膜叠层侧壁垂直度。 可以使用本文所述的方法和装置来制造具有越来越均匀和降低的临界尺寸的存储器单元。

公开(公告)号：US20220013716A1

公开(公告)日：2022-01-13

申请号：US17486649

申请日：2021-09-27

Applicant: Applied Materials, Inc.

Inventor： Lin XUE ,  Jaesoo AHN ,  Mahendra PAKALA ,  Chi Hong CHING ,  Rongjun WANG

IPC: H01L43/12 ,  H01L43/08 ,  H01L43/10 ,  H01F10/14 ,  H01F10/32

Abstract: Embodiments of the disclosure provide methods and apparatus for fabricating magnetic tunnel junction (MTJ) structures on a substrate in for spin-transfer-torque magnetoresistive random access memory (STT-MRAM) applications. In one example, a film stack utilized to form a magnetic tunnel junction structure on a substrate includes a pinned layer disposed on a substrate, wherein the pinned layer comprises multiple layers including at least one or more of a Co containing layer, Pt containing layer, Ta containing layer, an Ru containing layer, an optional structure decoupling layer disposed on the pinned magnetic layer, a magnetic reference layer disposed on the optional structure decoupling layer, a tunneling barrier layer disposed on the magnetic reference layer, a magnetic storage layer disposed on the tunneling barrier layer, and a capping layer disposed on the magnetic storage layer.

公开(公告)号：US20210351344A1

公开(公告)日：2021-11-11

申请号：US17379780

申请日：2021-07-19

Applicant: Applied Materials, Inc.

Inventor： Hsin-wei TSENG ,  Chando PARK ,  Jaesoo AHN ,  Lin XUE ,  Mahendra PAKALA

IPC: H01L43/12 ,  H01L27/22

Abstract: Embodiments of the disclosure provide methods and apparatus for fabricating magnetic tunnel junction (MTJ) structures on a substrate in for hybrid (or called integrated) spin-orbit-torque magnetic spin-transfer-torque magnetic random access memory (SOT-STT MRAM) applications. In one embodiment, the method includes one or more magnetic tunnel junction structures disposed on a substrate, the magnetic tunnel junction structure comprising a first ferromagnetic layer and a second ferromagnetic layer sandwiching a tunneling barrier layer, a spin orbit torque (SOT) layer disposed on the magnetic tunnel junction structure, and a back end structure disposed on the spin orbit torque (SOT) layer.

公开(公告)号：US20190172485A1

公开(公告)日：2019-06-06

申请号：US16272183

申请日：2019-02-11

Applicant: Applied Materials, Inc.

Inventor： Lin XUE ,  Chi Hong CHING ,  Jaesoo AHN ,  Mahendra PAKALA ,  Rongjun WANG

IPC: G11B5/39 ,  H01L21/768 ,  G11B5/31 ,  G11C11/15

Abstract: Embodiments herein provide methods of forming a magnetic tunnel junction structure. The method includes forming a film stack that includes: a buffer layer; a seed layer disposed over the buffer layer; a first pinning layer disposed over the seed layer; a synthetic ferrimagnet (SyF) coupling layer disposed over the first pinning layer; a second pinning layer disposed over the SyF coupling layer; a structure blocking layer disposed over the second pinning layer; a magnetic reference layer disposed over the structure blocking layer; a tunnel barrier layer disposed over the magnetic reference layer; a magnetic storage layer disposed over the tunnel barrier layer; a capping layer disposed over the magnetic storage layer; and a hard mask disposed over the capping layer, wherein at least one of the capping layer, the buffer layer, and the SyF coupling layer is not fabricated from Ru; and forming a magnetic tunnel junction structure.