公开(公告)号：US20180107240A1

公开(公告)日：2018-04-19

申请号：US15831732

申请日：2017-12-05

Applicant: Apple Inc.

Inventor： Shu-Yi Yu ,  Erik P. Machnicki ,  Gilbert H. Herbeck ,  Kiran B. Kattel ,  Manu Gulati

IPC: G06F1/12

CPC classification number: G06F1/12 ,  G06F1/14

Abstract: In an embodiment, an integrated circuit such as an SOC (or even a discrete chip system) includes one or more local timebases in various locations. The timebases may be incremented based on a high frequency local clock that may be subject to variation during use due. Periodically, based on a lower frequency clock that is subject to less variation, the local timebases may be synchronized to the correct time, using hardware circuitry. In particular, the correct timebase value for the next synchronization may be transmitted to each local timebase, and the control circuit for the local timebase may be configured to saturate the local timebase at the correct value if the local timebase reaches the correct value before the synchronization occurs. Similarly, if the synchronization occurs and the local timebase has not reached the correct value, the control circuit may be configured to load the correct timebase value.

公开(公告)号：US09645630B2

公开(公告)日：2017-05-09

申请号：US13745731

申请日：2013-01-18

Applicant: Apple Inc.

Inventor： Shane J. Keil ,  Erik P. Machnicki ,  Josh P. de Cesare

IPC: G06F1/00 ,  G06F9/00 ,  G06F1/32

CPC classification number: G06F1/3234 ,  G06F1/3203

Abstract: Techniques are disclosed relating to power management within an integrated circuits. In one embodiment an apparatus is disclosed that includes a circuit and a power management unit. The power management unit is configured to provide, based on a programmable setting, an indication of whether an attempted communication to the circuit is permitted to cause the circuit to exit from a power-managed state. In some embodiments, the apparatus includes a fabric configured to transmit the attempted communication to the circuit from a device. In such an embodiment, the circuit is configured to exit the power-managed state in response to receiving the attempted communication. The fabric is configured to determine whether to transmit the attempted communication based on the indication provided by the power management unit.

公开(公告)号：US09465740B2

公开(公告)日：2016-10-11

申请号：US13860885

申请日：2013-04-11

Applicant: Apple Inc.

Inventor： Erik P. Machnicki ,  Harshavardhan Kaushikkar ,  Shinye Shiu

IPC: G06F12/00 ,  G06F12/08

CPC classification number: G06F12/0828 ,  G06F2212/1008 ,  G06F2212/507

Abstract: An apparatus for processing coherency transactions in a computing system is disclosed. The apparatus may include a request queue circuit, a duplicate tag circuit, and a memory interface unit. The request queue circuit may be configured to generate a speculative read request dependent upon a received read transaction. The duplicate tag circuit may be configured to store copies of tag from one or more cache memories, and to generate a kill message in response to a determination that data requested in the received read transaction is stored in a cache memory. The memory interface unit may be configured to store the generated speculative read request dependent upon a stall condition. The stored speculative read request may be sent to a memory controller dependent upon the stall condition. The memory interface unit may be further configured to delete the speculative read request in response to the kill message.

Abstract translation: 公开了一种用于处理计算系统中的一致性事务的装置。 该装置可以包括请求队列电路，复制标签电路和存储器接口单元。 请求队列电路可以被配置为根据所接收的读取事务来生成推测性读取请求。 重复标签电路可以被配置为存储来自一个或多个高速缓冲存储器的标签的副本，并且响应于所接收的读取事务中请求的数据被存储在高速缓冲存储器中的确定来生成杀死消息。 存储器接口单元可以被配置为根据失速条件来存储产生的推测性读取请求。 存储的推测性读取请求可以根据失速条件发送到存储器控制器。 存储器接口单元还可以被配置为响应于杀死消息来删除推测性读取请求。

公开(公告)号：US20160291625A1

公开(公告)日：2016-10-06

申请号：US14673326

申请日：2015-03-30

Applicant: Apple Inc.

Inventor： Brijesh Tripathi ,  Eric G. Smith ,  Erik P. Machnicki ,  Jung Wook Cho ,  Khaled M. Alashmouny ,  Kiran B. Kattel ,  Vijay M. Bettada ,  Bo Yang ,  Wenlong Wei

IPC: G05F3/02

CPC classification number: G05F3/02 ,  G06F1/324 ,  G06F1/3296

Abstract: An under voltage detection circuit and method of operating an IC including the same is disclosed. In one embodiment, an IC includes an under voltage protection circuit having first and second comparators configured to compare a supply voltage to first and second voltage thresholds, respectively, with the second voltage threshold being greater than the first. A logic circuit is coupled to receive signals from the first and second comparators. During operation in a high performance state by a corresponding functional circuit, the logic circuit is configured to cause assertion of a throttling signal responsive to an indication that the supply voltage has fallen below the first threshold. A clock signal provided to the functional circuit may be throttled responsive to the indication. If the supply voltage subsequently rises to a level above the second threshold, the throttling signal may be de-asserted.

Abstract translation: 公开了一种欠压检测电路及其运算方法。 在一个实施例中，IC包括欠压保护电路，其具有第一和第二比较器，其被配置为分别将电源电压与第一和第二电压阈值进行比较，其中第二电压阈值大于第一电压阈值。 逻辑电路被耦合以从第一和第二比较器接收信号。 在通过相应的功能电路在高性能状态下操作期间，逻辑电路被配置为响应于电源电压已经低于第一阈值的指示而导致节流信号的断言。 提供给功能电路的时钟信号可以响应于指示而被节流。 如果电源电压随后上升到高于第二阈值的水平，则节流信号可以被取消断言。

公开(公告)号：US09354658B2

公开(公告)日：2016-05-31

申请号：US14468982

申请日：2014-08-26

Applicant: Apple Inc.

Inventor： Erik P. Machnicki ,  Shane J. Keil

IPC: G06F1/12 ,  H03K5/01 ,  H03K5/00

CPC classification number: G06F1/12 ,  H03K5/01 ,  H03K2005/00013

Abstract: An apparatus for synchronizing a signal from a first clock domain into a second clock domain is disclosed. The apparatus may include circuitry, a synchronization circuit, and a clock gate circuit. The circuitry may de-assert a first enable signal dependent upon a first clock signal. The synchronization circuit may generate a second enable signal synchronized to a second clock signal and may de-assert the second enable signal in response to de-asserting the first enable signal. The clock gate circuit may generate a third clock signal dependent upon the second clock signal, and may disable the third clock signal responsive to de-asserting the second enable signal. The circuitry may further disable the second clock signal in response to determining a predetermined period of time has elapsed since de-asserting the first enable signal.

Abstract translation: 公开了一种用于将来自第一时钟域的信号同步到第二时钟域的装置。 该装置可以包括电路，同步电路和时钟门电路。 电路可以取决于第一时钟信号取消置位第一使能信号。 同步电路可以产生与第二时钟信号同步的第二使能信号，并且可以响应于取消断言第一使能信号来取消断言第二使能信号。 时钟门电路可以产生取决于第二时钟信号的第三时钟信号，并且可以响应于取消断言第二使能信号来禁用第三时钟信号。 所述电路还可以响应于确定从所述第一使能信号解除所述已经经过的预定时间段来禁止所述第二时钟信号。

公开(公告)号：US20160048191A1

公开(公告)日：2016-02-18

申请号：US14459482

申请日：2014-08-14

Applicant: Apple Inc.

Inventor： Erik P. Machnicki ,  Gilbert H. Herbeck ,  Shu-Yi Yu ,  Sebastian Skalberg

IPC: G06F1/32

CPC classification number: G06F1/3237 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3287 ,  Y02D10/128 ,  Y02D10/171 ,  Y02D50/20

Abstract: A system and method for managing idleness of functional units in an IC is disclosed. An IC includes a subsystem having a number of functional units and an idle aggregation unit. When a particular functional unit determines that it is idle, it may assert an idle indication to the idle aggregation unit. When the respective idle indications are concurrently asserted for all of the functional units, the idle aggregation unit may assert and provide respective idle request signals to each of the functional units. Responsive to receiving an idle request unit, a given functional unit may provide an acknowledgement signal to the idle aggregation unit if no transactions are incoming. If all functional units have concurrently asserted their respective acknowledgement signals, the idle aggregation unit may provide an indication of the same to a clock gating unit, which may then gate the clock signal(s) received by the functional units.

Abstract translation: 公开了一种用于管理IC中的功能单元的空闲的系统和方法。 IC包括具有多个功能单元和空闲聚合单元的子系统。 当特定功能单元确定它是空闲时，它可以向空闲聚合单元断言空闲指示。 当对于所有功能单元同时断言相应的空闲指示时，空闲汇聚单元可以向每个功能单元断言并提供相应的空闲请求信号。 响应于接收空闲请求单元，如果没有事务进入，则给定功能单元可以向空闲聚合单元提供确认信号。 如果所有功能单元已经同时确定其各自的确认信号，则空闲聚合单元可以向时钟选通单元提供相同的指示，时钟门控单元然后可以对由功能单元接收的时钟信号进行门控。

公开(公告)号：US20160026234A1

公开(公告)日：2016-01-28

申请号：US14876922

申请日：2015-10-07

Applicant: Apple Inc.

Inventor： Erik P. Machnicki ,  Gurjeet S. Saund ,  Munetoshi Fukami ,  Shane J. Keil ,  Chaitanya Kosaraju ,  Erdem Guleyupoglu ,  Jason M. Kassoff ,  Kevin C. Wong

IPC: G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/3206 ,  G06F1/3246 ,  G06F1/329 ,  G06F1/3293 ,  Y02D10/24 ,  Y02D50/20

Abstract: A method and apparatus for interfacing dynamic hardware power managed blocks and software power managed blocks is disclosed. In one embodiment, and integrated circuit (IC) may include a number of power manageable functional units. The functional units maybe power managed through hardware, software, or both. Each of the functional units may be coupled to at least one other functional unit through a direct communications link. A link state machine may monitor each of the communications links between functional units, and may broadcast indications of link availability to the functional units coupled to the link. Responsive to a software request to shut down a given link, or a hardware initiated shutdown of one of the functional units coupled to the link, the link state machine may broadcast and indication that the link is unavailable.

Abstract translation: 公开了用于接口动态硬件功率管理块和软件功率管理块的方法和装置。 在一个实施例中，集成电路（IC）可以包括多个功率可管理的功能单元。 功能单元可以通过硬件，软件或两者进行功率管理。 每个功能单元可以通过直接通信链路耦合到至少一个其它功能单元。 链路状态机可以监视功能单元之间的每个通信链路，并且可以将链路可用性的指示广播到耦合到链路的功能单元。 响应于关闭给定链路的软件请求或耦合到链路的功能单元之一的硬件启动关机，链路状态机可以广播并指示链路不可用。

公开(公告)号：US20150347287A1

公开(公告)日：2015-12-03

申请号：US14458949

申请日：2014-08-13

Applicant: Apple Inc.

Inventor： Brijesh Tripathi ,  Shane J. Keil ,  Manu Gulati ,  Jung Wook Cho ,  Erik P. Machnicki ,  Gilbert H. Herbeck ,  Timothy J. Millet ,  Joshua P. De Cesare ,  Anand Dalal

IPC: G06F12/02 ,  G06F12/06

CPC classification number: G06F12/0223 ,  G06F1/3206 ,  G06F1/3287 ,  G06F1/3293 ,  G06F3/0625 ,  G06F3/0632 ,  G06F3/0634 ,  G06F3/0673 ,  G06F9/4406 ,  G06F12/0646 ,  G06F13/1668 ,  G06F13/4068 ,  G06F13/4265 ,  G06F2212/1032 ,  G11C11/40615 ,  Y02D10/122 ,  Y02D10/151 ,  Y02D10/171 ,  Y02D50/20

Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.

Abstract translation: 在一个实施例中，芯片上的系统（SOC）包括当SOC的其余部分断电时保持供电的组件。 该组件可以包括用于从各种设备传感器捕获数据的传感器捕获单元，并且可以对所捕获的传感器数据进行过滤。 响应于过滤，组件可以唤醒SOC的剩余部分以允许处理。 组件可以存储可编程配置数据，与SOC最近断电时的状态相匹配，用于SOC的其他组件，以便在唤醒后重新编程它们。 在一些实施例中，组件可以被配置为唤醒SOC内的存储器控​​制器和到存储器控制器的路径，以便将数据写入存储器。 SOC的其余部分可能仍然断电。

公开(公告)号：US20150323960A1

公开(公告)日：2015-11-12

申请号：US14468982

申请日：2014-08-26

Applicant: Apple Inc.

Inventor： Erik P. Machnicki ,  Shane J. Keil

IPC: G06F1/12 ,  H03K5/01

CPC classification number: G06F1/12 ,  H03K5/01 ,  H03K2005/00013

Abstract: An apparatus for synchronizing a signal from a first clock domain into a second clock domain is disclosed. The apparatus may include circuitry, a synchronization circuit, and a clock gate circuit. The circuitry may de-assert a first enable signal dependent upon a first clock signal. The synchronization circuit may generate a second enable signal synchronized to a second clock signal and may de-assert the second enable signal in response to de-asserting the first enable signal. The clock gate circuit may generate a third clock signal dependent upon the second clock signal, and may disable the third clock signal responsive to de-asserting the second enable signal. The circuitry may further disable the second clock signal in response to determining a predetermined period of time has elapsed since de-asserting the first enable signal.

Abstract translation: 公开了一种用于将来自第一时钟域的信号同步到第二时钟域的装置。 该装置可以包括电路，同步电路和时钟门电路。 电路可以取决于第一时钟信号取消置位第一使能信号。 同步电路可以产生与第二时钟信号同步的第二使能信号，并且可以响应于取消断言第一使能信号来取消断言第二使能信号。 时钟门电路可以产生取决于第二时钟信号的第三时钟信号，并且可以响应于取消断言第二使能信号来禁用第三时钟信号。 所述电路还可以响应于确定从所述第一使能信号解除所述已经经过的预定时间段来禁止所述第二时钟信号。

公开(公告)号：US20150113193A1

公开(公告)日：2015-04-23

申请号：US14590203

申请日：2015-01-06

Applicant: Apple Inc.

Inventor： Josh P. de Cesare ,  Ruchi Wadhawan ,  Erik P. Machnicki ,  Mark D. Hayter

IPC: G06F13/24

CPC classification number: G06F13/24 ,  G06F2213/2424 ,  Y02D10/14

Abstract: In one embodiment, an interrupt controller may implement an interrupt distribution scheme for distributing interrupts among multiple processors. The scheme may take into account various processor state in determining which processor should receive a given interrupt. For example, the processor state may include whether or not the processor is in a sleep state, whether or not interrupts are enabled, whether or not the processor has responded to previous interrupts, etc. The interrupt controller may implement timeout mechanisms to detect that an interrupt is being delayed (e.g. after being offered to a processor). The interrupt may be re-evaluated at the expiration of a timeout, and potentially offered to another processor. The interrupt controller may be configured to automatically, and atomically, mask an interrupt in response to delivering an interrupt vector for the interrupt to a responding processor.

Abstract translation: 在一个实施例中，中断控制器可以实现用于在多个处理器之间分配中断的中断分配方案。 该方案可以考虑在确定哪个处理器应该接收给定中断时的各种处理器状态。 例如，处理器状态可以包括处理器是否处于休眠状态，中断是否被使能，处理器是否响应先前的中断等。中断控制器可以实现超时机制以检测到 中断被延迟（例如，在提供给处理器之后）。 中断可能会在超时到期时重新评估，并可能提供给另一个处理器。 中断控制器可以被配置为自动并原子地屏蔽中断，以响应于将中断的中断向量传递给响应处理器。