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    Interrupt distribution scheme
    1.
    发明授权
    Interrupt distribution scheme 有权

    公开(公告)号：US09262353B2

    公开(公告)日：2016-02-16

    申请号：US14590203

    申请日：2015-01-06

    Applicant: Apple Inc.

    Inventor： Josh P. de Cesare ,  Ruchi Wadhawan ,  Erik P. Machnicki ,  Mark D. Hayter

    IPC: G06F13/24

    CPC classification number: G06F13/24 ,  G06F2213/2424 ,  Y02D10/14

    Abstract: In one embodiment, an interrupt controller may implement an interrupt distribution scheme for distributing interrupts among multiple processors. The scheme may take into account various processor state in determining which processor should receive a given interrupt. For example, the processor state may include whether or not the processor is in a sleep state, whether or not interrupts are enabled, whether or not the processor has responded to previous interrupts, etc. The interrupt controller may implement timeout mechanisms to detect that an interrupt is being delayed (e.g. after being offered to a processor). The interrupt may be re-evaluated at the expiration of a timeout, and potentially offered to another processor. The interrupt controller may be configured to automatically, and atomically, mask an interrupt in response to delivering an interrupt vector for the interrupt to a responding processor.

    Power Managed Lock Optimization
    3.
    发明申请
    Power Managed Lock Optimization 有权
    电力管理锁优化

    公开(公告)号：US20130067257A1

    公开(公告)日：2013-03-14

    申请号：US13669890

    申请日：2012-11-06

    Applicant: APPLE INC.

    Inventor： Josh P de Cesare ,  Ruchi Wadhawan ,  Michael J Smith ,  Puneet Kumar ,  Bernard J Semeria

    IPC: G06F9/46 ,  G06F1/32

    CPC classification number: G06F1/3228 ,  G06F9/526

    Abstract: In an embodiment, a timer unit may be provided that may be programmed to a selected time interval, or wakeup interval. A processor may execute a wait for event instruction, and enter a low power state for the thread that includes the instruction. The timer unit may signal a timer event at the expiration of the wakeup interval, and the processor may exit the low power state in response to the timer event. The thread may continue executing with the instruction following the wait for event instruction. In an embodiment, the processor/timer unit may be used to implement a power-managed lock acquisition mechanism, in which the processor is awakened a number of times to check the lock and execute the wait for event instruction if the lock is not free, after which the thread may block until the lock is free.

    Abstract translation: 在一个实施例中，可以提供可以被编程到所选择的时间间隔或唤醒间隔的定时器单元。 处理器可以执行等待事件指令，并为包括指令的线程输入低功率状态。 定时器单元可以在唤醒间隔期满时发送定时器事件，并且处理器可以响应于定时器事件而退出低功率状态。 线程可以在等待事件指令之后的指令继续执行。 在一个实施例中，处理器/定时器单元可以用于实现功率管理的锁获取机制，其中处理器被唤醒多次以检查锁定并且如果锁不是空闲的则执行等待事件指令， 之后，线程可能会阻塞，直到锁定为空。

    Dynamic QoS Upgrading
    4.
    发明申请
    Dynamic QoS Upgrading 有权
    动态QoS升级

    公开(公告)号：US20140052937A1

    公开(公告)日：2014-02-20

    申请号：US14062302

    申请日：2013-10-24

    Applicant: Apple Inc.

    Inventor： Sukalpa Biswas ,  Hao Chen ,  Ruchi Wadhawan

    IPC: G06F13/16

    CPC classification number: G06F13/1694 ,  G06F13/1684

    Abstract: In an embodiment, a memory controller includes multiple ports. Each port may be dedicated to a different type of traffic. In an embodiment, quality of service (QoS) parameters may be defined for the traffic types, and different traffic types may have different QoS parameter definitions. The memory controller may be configured to schedule operations received on the different ports based on the QoS parameters. In an embodiment, the memory controller may support upgrade of the QoS parameters when subsequent operations are received that have higher QoS parameters, via sideband request, and/or via aging of operations. In an embodiment, the memory controller is configured to reduce emphasis on QoS parameters and increase emphasis on memory bandwidth optimization as operations flow through the memory controller pipeline.

    Abstract translation: 在一个实施例中，存储器控制器包括多个端口。 每个端口可能专用于不同类型的流量。 在一个实施例中，可以为业务类型定义服务质量（QoS）参数，并且不同的业务类型可以具有不同的QoS参数定义。 存储器控制器可以被配置为基于QoS参数调度在不同端口上接收的操作。 在一个实施例中，当接收到具有较高QoS参数，经由边带请求和/或通过操作老化的后续操作时，存储器控制器可以支持QoS参数的升级。 在一个实施例中，存储器控制器被配置为当操作流过存储器控制器管线时，减少对QoS参数的强调并且增加对存储器带宽优化的重视。

    Interrupt Distribution Scheme
    5.
    发明申请
    Interrupt Distribution Scheme 审中-公开
    中断分配方案

    公开(公告)号：US20150113193A1

    公开(公告)日：2015-04-23

    申请号：US14590203

    申请日：2015-01-06

    Applicant: Apple Inc.

    Inventor： Josh P. de Cesare ,  Ruchi Wadhawan ,  Erik P. Machnicki ,  Mark D. Hayter

    IPC: G06F13/24

    CPC classification number: G06F13/24 ,  G06F2213/2424 ,  Y02D10/14

    Abstract: In one embodiment, an interrupt controller may implement an interrupt distribution scheme for distributing interrupts among multiple processors. The scheme may take into account various processor state in determining which processor should receive a given interrupt. For example, the processor state may include whether or not the processor is in a sleep state, whether or not interrupts are enabled, whether or not the processor has responded to previous interrupts, etc. The interrupt controller may implement timeout mechanisms to detect that an interrupt is being delayed (e.g. after being offered to a processor). The interrupt may be re-evaluated at the expiration of a timeout, and potentially offered to another processor. The interrupt controller may be configured to automatically, and atomically, mask an interrupt in response to delivering an interrupt vector for the interrupt to a responding processor.

    Abstract translation: 在一个实施例中，中断控制器可以实现用于在多个处理器之间分配中断的中断分配方案。 该方案可以考虑在确定哪个处理器应该接收给定中断时的各种处理器状态。 例如，处理器状态可以包括处理器是否处于休眠状态，中断是否被使能，处理器是否响应先前的中断等。中断控制器可以实现超时机制以检测到 中断被延迟（例如，在提供给处理器之后）。 中断可能会在超时到期时重新评估，并可能提供给另一个处理器。 中断控制器可以被配置为自动并原子地屏蔽中断，以响应于将中断的中断向量传递给响应处理器。

    Dynamic QoS upgrading
    6.
    发明授权
    Dynamic QoS upgrading 有权

    公开(公告)号：US08762653B2

    公开(公告)日：2014-06-24

    申请号：US14062302

    申请日：2013-10-24

    Applicant: Apple Inc.

    Inventor： Sukalpa Biswas ,  Hao Chen ,  Ruchi Wadhawan

    IPC: G06F12/00

    CPC classification number: G06F13/1694 ,  G06F13/1684

    Abstract: In an embodiment, a memory controller includes multiple ports. Each port may be dedicated to a different type of traffic. In an embodiment, quality of service (QoS) parameters may be defined for the traffic types, and different traffic types may have different QoS parameter definitions. The memory controller may be configured to schedule operations received on the different ports based on the QoS parameters. In an embodiment, the memory controller may support upgrade of the QoS parameters when subsequent operations are received that have higher QoS parameters, via sideband request, and/or via aging of operations. In an embodiment, the memory controller is configured to reduce emphasis on QoS parameters and increase emphasis on memory bandwidth optimization as operations flow through the memory controller pipeline.

    Power managed lock optimization
    7.
    发明授权
    Power managed lock optimization 有权
    电源管理锁优化

    公开(公告)号：US08578079B2

    公开(公告)日：2013-11-05

    申请号：US13669890

    申请日：2012-11-06

    Applicant: Apple Inc.

    Inventor： Josh P de Cesare ,  Ruchi Wadhawan ,  Michael J Smith ,  Puneet Kumar ,  Bernard J Semeria

    IPC: G06F13/00 ,  G06F1/32

    CPC classification number: G06F1/3228 ,  G06F9/526

    Abstract: In an embodiment, a timer unit may be provided that may be programmed to a selected time interval, or wakeup interval. A processor may execute a wait for event instruction, and enter a low power state for the thread that includes the instruction. The timer unit may signal a timer event at the expiration of the wakeup interval, and the processor may exit the low power state in response to the timer event. The thread may continue executing with the instruction following the wait for event instruction. In an embodiment, the processor/timer unit may be used to implement a power-managed lock acquisition mechanism, in which the processor is awakened a number of times to check the lock and execute the wait for event instruction if the lock is not free, after which the thread may block until the lock is free.

    Abstract translation: 在一个实施例中，可以提供可以被编程到所选择的时间间隔或唤醒间隔的定时器单元。 处理器可以执行等待事件指令，并为包括指令的线程输入低功率状态。 定时器单元可以在唤醒间隔期满时发送定时器事件，并且处理器可以响应于定时器事件而退出低功率状态。 线程可以在等待事件指令之后的指令继续执行。 在一个实施例中，处理器/定时器单元可以用于实现功率管理的锁获取机制，其中处理器被唤醒多次以检查锁定并且如果锁不是空闲的则执行等待事件指令， 之后，线程可能会阻塞，直到锁定为空。

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