公开(公告)号：US20150113193A1

公开(公告)日：2015-04-23

申请号：US14590203

申请日：2015-01-06

Applicant: Apple Inc.

Inventor： Josh P. de Cesare ,  Ruchi Wadhawan ,  Erik P. Machnicki ,  Mark D. Hayter

IPC: G06F13/24

CPC classification number: G06F13/24 ,  G06F2213/2424 ,  Y02D10/14

Abstract: In one embodiment, an interrupt controller may implement an interrupt distribution scheme for distributing interrupts among multiple processors. The scheme may take into account various processor state in determining which processor should receive a given interrupt. For example, the processor state may include whether or not the processor is in a sleep state, whether or not interrupts are enabled, whether or not the processor has responded to previous interrupts, etc. The interrupt controller may implement timeout mechanisms to detect that an interrupt is being delayed (e.g. after being offered to a processor). The interrupt may be re-evaluated at the expiration of a timeout, and potentially offered to another processor. The interrupt controller may be configured to automatically, and atomically, mask an interrupt in response to delivering an interrupt vector for the interrupt to a responding processor.

Abstract translation: 在一个实施例中，中断控制器可以实现用于在多个处理器之间分配中断的中断分配方案。 该方案可以考虑在确定哪个处理器应该接收给定中断时的各种处理器状态。 例如，处理器状态可以包括处理器是否处于休眠状态，中断是否被使能，处理器是否响应先前的中断等。中断控制器可以实现超时机制以检测到 中断被延迟（例如，在提供给处理器之后）。 中断可能会在超时到期时重新评估，并可能提供给另一个处理器。 中断控制器可以被配置为自动并原子地屏蔽中断，以响应于将中断的中断向量传递给响应处理器。

公开(公告)号：US09262353B2

公开(公告)日：2016-02-16

申请号：US14590203

申请日：2015-01-06

Applicant: Apple Inc.

Inventor： Josh P. de Cesare ,  Ruchi Wadhawan ,  Erik P. Machnicki ,  Mark D. Hayter

IPC: G06F13/24

CPC classification number: G06F13/24 ,  G06F2213/2424 ,  Y02D10/14

Abstract: In one embodiment, an interrupt controller may implement an interrupt distribution scheme for distributing interrupts among multiple processors. The scheme may take into account various processor state in determining which processor should receive a given interrupt. For example, the processor state may include whether or not the processor is in a sleep state, whether or not interrupts are enabled, whether or not the processor has responded to previous interrupts, etc. The interrupt controller may implement timeout mechanisms to detect that an interrupt is being delayed (e.g. after being offered to a processor). The interrupt may be re-evaluated at the expiration of a timeout, and potentially offered to another processor. The interrupt controller may be configured to automatically, and atomically, mask an interrupt in response to delivering an interrupt vector for the interrupt to a responding processor.