US11336501B2
[Task] There is provided a signal generation apparatus and a signal generation method capable of performing mutual switching between a PAM N signal having n values and a PAM M signal having m values (m
US11336498B2
A transmitter includes a mapping circuit and a framing circuit. The mapping circuit is configured to combine and map a first data sequence and a second data sequence onto orthogonal frequency division multiplexing (OFDM) subcarriers which include first subcarriers and second subcarriers. The framing circuit is configured to generate an OFDM signal from the OFDM subcarriers. The mapping circuit is configured to: map first data included in the first data sequence and second data included in the second data sequence onto the first subcarriers; and map the second data onto the second subcarriers. The first data are not mapped on the second subcarriers.
US11336494B2
A method and apparatus for generating a signal in a wireless communication system is provided. A user equipment (UE) which operates in a new radio access technology (RAT) generates a signal for a numerology based on a center frequency of a carrier, and transmits the generated signal. The center frequency of the carrier is based on a largest subcarrier spacing that a network supports.
US11336487B1
A system and method for optimizing a channel sounding procedure of a multi-link device (MLD) is disclosed. The improved channel sounding procedure disclosed herein involves an MLD requesting channel sounding information from a group of receivers on a first channel representing a first physical frequency, but receiving channel sounding information from a subgroup of the receivers on one or more other channels representing different physical frequencies. In this manner, the channel sounding procedure on a specific link of an MLD is optimized by offloading some of the sounding process to a different radio link that is also operational for the MLD as part of the same association context.
US11336486B2
Some embodiments provide a method for a set of central controllers that manages forwarding elements operating in a plurality of datacenters. The method receives a configuration for a bridge between (i) a logical L2 network that spans at least two datacenters and (ii) a physical L2 network. The configuration specifies a particular one of the datacenters for implementation of the bridge. The method identifies multiple managed forwarding elements that implement the logical L2 network and are operating in the particular datacenter. The method selects one of the identified managed forwarding elements to implement the bridge. The method distributes bridge configuration data to the selected managed forwarding element.
US11336483B2
Directional wireless drop systems are provided. These systems include a tap unit that is connected to a communications line of the broadband network; a cable modem unit connected to the tap unit; a plurality of wireless routers connected to the cable modem unit; and a directional antenna unit that is connected to at least a first of the wireless routers. Each wireless router is associated with a respective one of a plurality of subscriber premises that are served by the directional wireless drop system and is configured to communicate with at least one device that is located at the respective one of plurality of subscriber premises.
US11336482B2
Techniques are described for policy driven on-demand tunnel creation and deletion between end points in a software-defined wide area network (SD-WAN) having a hub-and-spoke topology. A software-defined networking (SDN) controller that facilitates cloud-based services of a service provider network that sets up the SD-WAN is configured to determine whether a tunnel between end-points is to be created or deleted based on information indicative of the traffic, such as amount, time, application generating the traffic, and the like, between end-points.
US11336470B2
An operation method of a first end node of an Ethernet-based vehicle network is provided. The operation method includes detecting a local event and transitioning an operation state of a physical layer (PHY) of the first end node from a sleep state to a wake-up state. A pseudo PHY identifier (ID) is configured as a PHY ID of the first end node in response to the first end node operating in the wake-up state. A first beacon including the pseudo PHY ID is then transmitted and the first beacon indicates that the first end node operates in the wake-up state.
US11336466B1
A method, in a provisioning server, of provisioning a printer, includes: receiving a provisioning request from the printer, the provisioning request containing (i) a printer identifier, and (ii) an account identifier associated with the printer; obtaining, from a digital certificate issuer, a unique string; sending the unique string to the printer; receiving from the printer, in response to sending the unique string, a certificate signing request containing (i) the printer identifier, (ii) the account identifier, and (iii) an authentication token including the unique string signed with a private key of the printer; validating the certificate signing request; passing the validated certificate signing request to the digital certificate issuer; receiving, from the digital certificate issuer, a digital certificate encoding the printer identifier and the account identifier; and providing the digital certificate to the printer for storage.
US11336465B2
Disclosed herein are computer-implemented methods; computer-implemented systems; and non-transitory, computer-readable media, for sending cross-chain messages. One computer-implemented method includes storing an authenticable message (AM) associated with a first account to a blockchain associated with the first blockchain network, where the AM is generated based on a protocol stack comprising an outer-layer protocol, a middle-layer protocol, and an inner-layer protocol, the outer-layer protocol comprises an identifier (ID) of an originating blockchain network and the middle-layer protocol, the middle-layer protocol comprises information of the sending account and the inner-layer protocol, the inner-layer protocol comprises an ID of a destination blockchain network, information of a receiving account associated with the destination blockchain network, and message content. The AM and location information is transmitted to a relay to be forwarded to the second account associated with the second blockchain network.
US11336462B1
Systems, apparatuses, methods, and computer program products are disclosed for quantum computing (QC) detection. An example method includes generating QC detection data. The example method further includes generating a pair of asymmetric cryptographic keys comprising a public cryptographic key and a private cryptographic key, generating encrypted QC detection data based on the pair of asymmetric cryptographic keys, and destroying the private cryptographic key. The example method further includes monitoring a set of data environments for electronic information related to the encrypted QC detection data. Subsequently, the example method may include generating a QC detection alert control signal in response to detection of the electronic information related to the encrypted QC detection data.
US11336451B2
Examples of a method and apparatus for cross-chain resource transmission are described. The cross-chain resource transmission includes sending from a first account of a first blockchain to another blockchain. One example of the method is executed by the first blockchain and includes: initiating, by the first account, a first transaction used for cross-chain resource transmission, to decrement a first resource balance of the first account by a first quantity and save first data obtained through a consensus into the first blockchain based on execution of the first transaction, where the first data includes an authenticable message; and sending the first data and first location information to the relay end, which is used to send the authenticable message to the second blockchain, where a second resource balance of the second account is incremented by a second quantity.
US11336450B2
An embodiment of the present invention is directed to delivering an entitlements model that scales to both mid-frequency and low-latency use cases. The innovative solution may be distributed in nature and able to operate in low priority threads alongside the main logic of the software. An embodiment of the present invention may be implemented as a software module with APIs for ease of adoption.
US11336446B2
The present invention is an platform and/or agnostic authentication method and system operable to authenticate users, data, documents, device and transactions. Embodiments of the present invention may be operable with any client system. The authentication method and system are operable to disburse unique portions of anonymous login related information amongst multiple devices. These devices and the disburse unique portions of anonymous login information are utilized by the solution to authenticate users, data, documents, device and transactions. Login-related information is not stored in any portion of the solution, users and devices are anonymously authenticated. The solution also permits a user to access secured portions of the client system through a semi-autonomous process and without having to reveal the user's key.
US11336444B2
Disclosed herein are a hardware security module, a device having the hardware security module, and a method for operating the device. The method for verifying integrity of executable code in a device includes dividing, by a Micro-Control Unit (MCU), executable code into multiple blocks, generating, by the MCU, hash values corresponding to the blocks resulting from the division, storing, by a Hardware Security Module (HSM), the generated hash values, calculating, by the MCU, at least one hash value, among hash values of the multiple blocks when the executable code boots, and comparing, by the HSM, the calculated hash value with a hash value corresponding to the calculated hash value, among the hash values stored in the HSM.
US11336442B2
Traditional key generation methods in a noisy network often assume trusted devices and are thus vulnerable to many attacks including covert channels. The present invention differs from previous key generation schemes in that it presents a mechanism which allows secure key generation with untrusted devices in a noisy network with a prescribed access structure.
US11336425B1
Digital n-state switching devices are characterized by n-state switching tables with n greater than 4. N-state switching tables are transformed by a Finite Lab-transform (FLT) into an FLTed n-state switching table. Memory devices, processors and combinational circuits with inputs and an output are characterized by an FLTed n-state switching table and perform switching operations between physical states in accordance with an FLTed n-state switching table. The devices characterized by FLTed n-state switching tables are applied in cryptographic devices. The cryptographic devices perform standard cryptographic operations or methods that are modified in accordance with an FLT. One or more standard cryptographic methods are specified in Federal Information Processing Standard (FIPS) Publications. Security is improved by at least a factor n2.
US11336422B2
Embodiments of the present disclosure relate to methods and devices for data transmission. In example embodiments, a method implemented in a network device is provided. According to the method, a target RS port group is determined from a plurality of RS ports for transmitting a RS. The RS ports are associated with at least one network device. Then, a configuration of the target RS port group is transmitted to the terminal device.
US11336421B2
The present invention pertains to a wireless communication system, and more particularly, to a method of receiving a downlink (DL) control channel in a wireless communication system and an apparatus therefor, and the method comprises the following steps: receiving a radio resource control (RRC) message including resource block (RB) allocation information; receiving a subframe having a plurality of physical RBs; and monitoring a plurality of downlink control channel candidates in a physical RB set corresponding to the RB allocation information from the plurality of physical RBs to detect a downlink control channel allocated to a communication device, wherein the plurality of downlink control channel candidates do not continuously exist in a virtual RB set corresponding to the physical RB set.
US11336418B2
The present invention discloses a data transmission method and apparatus. The method comprises: determining on a terminal side whether there is an overlap between a transmission time of an uplink channel which transmits using a first transmission time interval length and a transmission time of an uplink channel which transmits using a second transmission time interval length; when there is an overlap, then selecting a part of the uplink channel for transmission according to a predetermined rule, and abandoning the remaining uplink channel for transmission or puncturing the transmission of the remaining uplink channel. On a network side, determining that the terminal selects one type of uplink channel for transmission according to the predetermined rule, and abandons another type of uplink channel for transmission or punctures the transmission of another type of uplink channel. With the present invention, correct transmission of the terminal can be achieved even when channels with different transmission time intervals overlap.
US11336416B2
Methods and apparatuses in a communication system, are provided. The solution comprises controlling (300) a connection to a user terminal having connections to more than one cell for carrier aggregation, controlling (302) transmission of signalling to the user terminal to use maximum allowable number of bits of hybrid automatic request feedback in transmission of positive and negative acknowledgements to more than one aggregated cell, controlling (304) reception of feedback bits from the user terminal, the feedback bits comprising positive and negative acknowledgements related to user terminal connections with the more than one aggregated cell, decoding (306) and processing feedback bits related to the connections controlled by the apparatus and transmitting (308) feedback bits related to other connections to respective cell.
US11336415B2
A system and method for multiplexing traffic. A wireless device such as a user equipment (UE) may receive a first signal over first resources assigned to carry a first downlink transmission from a base station, and receive a first downlink control indication (DCI) message from the base station. The first DCI message may include a pre-emption region (PR) indication and a PR bitmap, and the PR indication may indicate a location of a time-frequency region. The PR bitmap may include bits associated with different portions of the time-frequency region, and each of the bits in the PR bitmap may indicate whether a preemptive downlink transmission is present in the corresponding portion of the time-frequency region.
US11336413B2
A method and a device, which: receive, from a base station through a demodulation reference signal (DMRS) symbol, a DMRS set according to a specific pattern by the base station, wherein the DMRS is transmitted in a specific antenna port and positioned on one or two time axis symbols, which are the same as at least one other DMRS transmitted in another antenna port; and decode data by using the DMRS.
US11336412B2
Examples synchronization signal configuration methods and apparatus are described. One example method is applied to a relay network including a first node and a second node, and the first node is a parent node of the second node. The example method includes sending synchronization signal configuration information by the first node to the second node, where the synchronization signal configuration information is used to indicate M first synchronization signal time-frequency positions and N second synchronization signal time-frequency positions in a candidate synchronization signal time-frequency position set. The first synchronization signal time-frequency position is used by the second node to send a first synchronization signal, the second synchronization signal time-frequency position is used by the second node to receive or detect a second synchronization signal, the candidate synchronization signal time-frequency position set includes W synchronization signal time-frequency positions, and W≥(M+N).
US11336409B2
An apparatus and method for allocating time-frequency resource, comprising: allocating a first group-specific data time-frequency resource to data sequences associated to UEs comprised in a first UE group of the plurality of UE groups; and allocating a second group-specific data time-frequency data resource to data sequences associated to UEs comprised in a second UE group of the plurality of UE groups; wherein the first and the second group-specific data time-frequency resources at least partly overlap in time domain.
US11336400B2
A base station may cancel or delay (e.g., pre-empt) a transmission from a wireless device by sending a pre-emption indication to the wireless device. Based on receiving the pre-emption indication, the wireless device may cancel the transmission, store an indication associated with the cancelled transmission, and/or store the cancelled transmission in a data buffer. The base station may request transmission of the data unit (e.g., at a later time) by transmitting another indication.
US11336399B2
Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a transmitter device may transmit a hybrid automatic repeat request (HARQ) communication using a first code block order for code blocks of the HARQ communication; detect a trigger to retransmit the HARQ communication based at least in part on transmitting the HARQ communication; reorder the code blocks of the HARQ communication based at least in part on detecting the trigger to retransmit the HARQ communication; and retransmit the HARQ communication using a second code block order based at least in part on reordering the code blocks of the HARQ communication. Numerous other aspects are provided.
US11336397B2
A HAQR feedback method includes: receiving data transmitted from a transmitting end in a unit of a transmission block (TB), which includes a plurality of resource units; generating HARQ feedback information based on the resource units according to a pre-configured HARQ feedback policy, and returning the HARQ feedback information to the transmitting end, wherein the amount of feedback information units of the HARQ feedback information is smaller than the amount of the resource units contained in the TB.
US11336396B2
The present invention relates to a wireless communication system and, more particularly, to a method and an apparatus therefor, the method comprising the steps of: identifying a minimum storing area per data in a HARQ buffer on the basis of a TTI length; storing data for transmission of a wireless signal in the HARQ buffer on the basis of the minimum storing area per data; and transmitting the data in the HARQ buffer during a first TTI, wherein, when the data is retransmitted data, the minimum storing area per data is based on the length of a second TTI used for initial transmission of the data, and the length of the second TTI is different from the length of the first TTI.
US11336384B2
Transmitting, by the network device, the configuration information to a user equipment, wherein the configuration information is used to instruct the user equipment to use a measurement set to measure a synchronization signal, wherein the measurement set is used by a user equipment in a connected state to measure a synchronization signal, the measurement set is a first synchronization signal block (SS block) set, and the first SS block set includes a number of SS blocks smaller than a number of SS blocks included in a second SS block set which includes an SS block used by the user equipment in an idle state to measure the synchronization signal; or the measurement set is a signal set, and the signal set includes a part of signals in Y SS blocks, and Y is a positive integer.
US11336382B2
A terminal is disclosed including a receiver that receives a demodulation reference signal; and a processor that controls reception of the demodulation reference signal based on a parameter related to mapping of the demodulation reference signal, wherein when the parameter is configured to a specific value, a specific multiplexing method for the demodulation reference signal is supported. In other aspects, another terminal is also disclosed.
US11336370B1
An integrated transmitter chip comprising: at least one input port disposed at a first end; a first variable power divider optically connected to a first input port of the at least one input port, the first variable power divider being tunable to a first splitting ratio; a second and a third variable power dividers each optically connected to the first variable power divider, the second and the third variable power dividers being tunable to a second and a third splitting ratios; and a first and a second optical channels being optically branched from the second variable power divider, and a third and a fourth optical channels being optically branched from the third variable power divider; wherein an optical signal being launched into the first input port and having an input power is caused to be split by the first variable power divider into a first and a second optical signals.
US11336366B2
In response to a determination that network communication traffic at a network node relates to an emergency communication, a network controller can be operable to analyze a network condition associated with the network node. Based on an analysis of the network condition, the network controller can facilitate an adjustment to a partition of an integrated access and backhaul link. The network controller can further be operative to determine whether an operator policy is applicable to the adjustment of the partition. Additionally, the network controller can be operable to facilitate the selection of a path to route the emergency communication based upon the network condition and the operator policy.
US11336364B1
Satellites provide communication between devices such as user terminals and gateways to other networks, such as the Internet. Non-geosynchronous orbit satellites move relative to terrestrial user terminals, passing in and out of communication over time. To maintain ongoing communication, a handover takes place in which the responsibility to maintain communication with a particular user terminal passes from one satellite to another. To minimize disruption due to the handover, satellite motion and availability of communication resources are allocated in advance. Participating devices such as the user terminal, current satellite, and next satellite, are provided with details of the handover in advance. As a result, interruption in communication due to a handover from one satellite to another is substantially reduced.
US11336362B2
A repeater system includes a first repeater device to receive a first beam of radio frequency (RF) signal from a first network node, and a second repeater device to receive a second beam of RF signal from the first network node. The first repeater device synchronizes and controls the second repeater device to concurrently provide the first beam and the second beam of RF signal to a second network node. A plurality of measurements associated with network nodes and repeater devices is acquired. A plurality of signal parameters is selected at the first and second repeater devices for a first beam and a second beam of RF signal, respectively, such that a cross-leakage of first beam on the second beam of RF signal and vice-versa at the second network node is reduced and the gain and a phase of first beam and the second beam of RF signal is adjusted.
US11336361B2
Reducing the effects of path loss in millimeter wave (mmWave) directional communications by performing channel measurements estimating non-line of sight (NLOS) blockages, to determine angle-of-departure (AoD) and angle-of-arrival (AoA) and gain of identified paths so that directional antennas can be reconfigured to overcome unfavorable propagation conditions and reduce path losses.
US11336356B2
Embodiments of the present disclosure relate to methods, devices, apparatuses and computer readable storage media for Uplink Control Information (UCI) design. The method comprises determining, at a terminal device, a matrix comprising a set of non-zero linear combination coefficients for quantizing a channel between the terminal device and a network device, the matrix having spatial components and frequency components; shifting the frequency components of the matrix circularly, such that a target coefficient of the set of non-zero linear combination coefficients is located in a frequency component with a predetermined index of the frequency components in a shifted matrix; generating a first indication indicating the spatial component associated with the target coefficient in the matrix; and transmitting, to the network device, uplink control information comprising the first indication. In this way, a new solution for designing the UCI may reduce the overhead for reporting the parameters in the UCI.
US11336355B2
Certain aspects of the present disclosure provide techniques for channel quality indicator (CQI)-based downlink buffer management as well as mitigating throughput loss in dual connectivity with multi-SIM. A method that may be performed by a user equipment (UE) includes communicating with a first network on a first channel using a first technology, determining whether a tune-away associated with the first technology will occur, and outputting, for transmission to the first network on a second channel using a second technology, a channel quality indicator (CQI) report corresponding to the second channel if the tune-away will occur, wherein the CQI report indicates a lower CQI for the second channel than a current CQI for the second channel.
US11336347B2
Embodiments of this disclosure provide techniques for determining a device's beam correspondence status. As used herein, a device is considered to have “beam correspondence” when the device's TX and RX antennas satisfy a calibration criteria. In one example, a device's TX and RX antennas satisfy the calibration criteria when a difference between quality parameters corresponding to reference signals transmitted and received using corresponding TX and RX beams is less than a threshold. In another example, a device's TX and RX antennas satisfy the calibration criteria when a list of indices ranking the device's TX beams matches a list of indices ranking the device's RX beams. The lists of indices may be derived by transmitting and receiving references signals according to the devices RX and TX beams, and then generating list of indices based on quality parameters of the respective RX and TX beams.
US11336342B2
Radio apparatuses and methods for MIMO matrix phasing that may be used to toggle and/or weight the amount of MIMO processing based on the detected level of isolation between different polarizations of the system. Also described herein are apparatuses including auto-range and/or auto-scaling of a signal strength indicator to aid in precise alignment of the apparatus. Any of these apparatuses and methods may also include dynamic power boosting that adjusts the power (e.g., power amplifier) for an RF apparatus based on the data rate. These apparatuses may include a housing enclosing the radio device that includes a plurality of pin elements that may act as heat transfer pins and a ground pin for making a ground connection to the post or pole to which the devices is mounted.
US11336341B2
An apparatus includes a first communication device with multiple antennas, operably coupled to a processor and configured to access a codebook of transformation matrices. The processor generates a set of symbols based on an incoming data, and applies a permutation to each of the symbols to produce a set of permuted symbols. The processor transforms each of the permuted symbols based on at least one primitive transformation matrix, to produce a set of transformed symbols. The processor applies, to each of the transformed symbols, a precode matrix selected from the codebook of transformation matrices to produce a set of precoded symbols. The codebook of transformation matrices is accessible to a second communication device. The processor sends a signal to cause transmission, to the second communication device, of multiple signals, each representing a precoded symbol from the set of precoded symbols, each of the signals transmitted using a unique antenna from the plurality of antennas.
US11336332B2
A device for a handle of a motor vehicle door. The device includes, integrated into the door, a primary module that supplies power by inductive coupling to a secondary module integrated into the handle. The primary module includes a primary coil and the secondary module having a secondary coil positioned facing the primary coil. The secondary coil also serves as a repeater for contactless communication between the primary module and a terminal. If the handle is retractable, the device also allows the position of the handle during its movement between a deployed position and a retracted position to be estimated.
US11336329B2
A terminal apparatus includes a receiver and a transmitter. The receiver is configured to receive a radio resource control (RRC) parameter and a physical downlink control channel (PDCCH) including a downlink control information (DCI) format and scheduling a physical uplink shared channel (PUSCH). The transmitter is configured to transmit the PUSCH with frequency hopping within one slot. The RRC parameter indicates one or a plurality of frequency offset values. The PUSCH includes a first frequency hop and a second frequency hop within the one slot. In a case that a cyclic redundancy check (CRC) scrambled with or other than a temporary cell-radio network temporary identifier (TC-RNTI) is added to the DCI format, a frequency offset between the first frequency hop and the second frequency hop is based on a size of an initial uplink (UL) bandwidth part (BWP) or the RRC parameter, respectively.
US11336327B2
Techniques and apparatuses are described for enabling base stations (121, 122) to coordinate for canceling cross-link interference (380). The techniques and apparatuses described herein overcome challenges that a single base station (121) might otherwise face in trying to compensate a reception (131) by the base station (121) for cross-link interference (382) from a transmission (132) by another base station (122). The techniques and apparatuses described herein enable the base stations (121, 122) to form coordination sets to exchange information to enable the base stations (121, 122) to accurately reconstruct cross-link interference (380) and ultimately cancel the cross-link interference (380) to improve link quality.
US11336326B2
A communications apparatus includes a phase correction unit, a first radio frequency channel, a first analog bridge, a second radio frequency channel, and a second analog bridge. A first signal is sent to a first input end using the first radio frequency channel, and is divided into at least two channels of first sub-signals by using the first analog bridge. The at least two channels of first sub-signals are respective output from at least two first output ends to at least two first antenna arrays. Similarly, a second signal is divided into at least two channels of second sub-signals by using the second analog bridge, and the at least two channels of second sub-signals are output to at least two second antenna arrays. A first channel of first sub-signal and a first channel of second sub-signal are coupled to the phase correction unit by using a coupler.
US11336324B2
A high-frequency module includes a transmission signal amplifier that outputs a transmission signal to an antenna terminal side; a reception signal amplifier that amplifies a reception signal supplied from an antenna terminal; a switch that selectively connects the antenna terminal to either an output of the transmission signal amplifier or an input of the reception signal amplifier; and a directional coupler that is provided on a transmission signal path and detects a signal level of the transmission signal. The transmission signal amplifier is controlled by a first control signal supplied from a first control circuit. The reception signal amplifier is controlled by a second control signal supplied from a second control circuit. The switch is controlled by a switch control signal supplied from the first control circuit. The directional coupler is controlled by a coupler control signal supplied from the first control circuit.
US11336319B2
A circuit arrangement including one or more processors configured to: detect a presence of one or more human object proximities based on sensor data; identify one or more coverage sectors of one or more antenna arrays, operably coupled to the one or more processors, in response to the detected presence of the one or more human object proximities; determine whether radio waves within the one or more identified coverage sectors satisfy a transmit power criteria; select one or more candidate coverage sectors of the one or more antenna arrays based the one or more identified coverage sectors; and determine at least one radio link quality for the radio waves of the one or more candidate coverage sectors.
US11336316B2
An apparatus comprising: a sampler for over-sampling an input signal to produce a sampled input signal; a delta-sigma modulator for modulating the sampled input signal to produce a modulated signal; and a filter for filtering the modulated signal, the filter comprising: a conductive patch and a ground plane separated by a dielectric wherein the ground plane comprises a band-gap periodic structure.
US11336314B2
A radio frequency, RF, transmitter, comprises a digitally controlled oscillator, DCO, configured to generate an RF signal; and digital modulation circuitry connected to the DCO for modulation of the RF signal, and driven by an RF clock signal derived from the RF signal, wherein the digital modulation circuitry comprises a module configured to apply a compensation for modulation jitter due to the modulation circuitry being driven by the RF clock signal and a compensation for DCO non-linearity.
US11336311B2
Disclosed is an electronic device including an antenna module comprising a plurality of radio frequency (RF) chains, and a processor configured to control the antenna module, wherein each of the RF chains comprises an amplifier that amplifies power and a power detector, and wherein the antenna module further comprises a switching circuit that selectively switches between a first path and a second path, the first path being a connection through which an RF signal converted in the antenna module is transmitted to the power detector causing the RF signal to be detected, and the second path being a connection through which the RF signal is transmitted to the amplifier causing the power detector to detect an RF signal of the amplifier.
US11336303B2
A digital system, components and method are configured with nonvolatile memory for storing digital data using codewords. The data is stored in the memory using multiple bits per memory cell of the memory. A code efficiency, for purposes of write operations and read operations relating to the memory, can be changed on a codeword to codeword basis based on input parameters. The code efficiency can change based on changing any one of the input parameters including bit density that is stored by the memory. Storing and reading fractional bit densities is described.
US11336298B2
Methods, systems, and devices for operating a memory device are described. An error correction bit flipping scheme may include methods, systems, and devices for performing error correction of one or more bits (e.g., a flip bit) and for efficiently communicating error correction information. The data bits and the flip bit (e.g., an error corrected flip bit) may be directly transmitted (e.g., to a flip decision component). The flip bit may be transmitted to the flip decision component over a dedicated and/or unidirectional line that is different from one or more other lines that carry data bits (e.g., to the flip decision component).
US11336296B2
The present technology includes a controller and a memory system including the same. The controller includes a memory interface configured to receive a codeword from a memory device, and an error correction circuit configured to: perform an error correction decoding operation on the codeword received from the memory interface, compare a number of unsatisfied check nodes (UCNs) detected in the error correction decoding operation with a reference number, perform or stop the error correction decoding operation on the codeword according to a result of comparing the number of UCNs and the reference number, and output a retransmission request signal of the codeword to the memory interface in response to the result, wherein the memory interface requests the codeword to the memory device in response to the retransmission request signal.
US11336287B1
An integrated circuit can include a data processing engine (DPE) array having a plurality of tiles. The plurality of tiles can include a plurality of DPE tiles, wherein each DPE tile includes a stream switch, a core configured to perform operations, and a memory module. The plurality of tiles can include a plurality of memory tiles, wherein each memory tile includes a stream switch, a direct memory access (DMA) engine, and a random-access memory. The DMA engine of each memory tile may be configured to access the random-access memory within the same memory tile and the random-access memory of at least one other memory tile. Selected ones of the plurality of DPE tiles may be configured to access selected ones of the plurality of memory tiles via the stream switches.
US11336286B2
A method includes detecting an open in a first IO element of a first bank of IOs and not in a second bank of IOs. The first and second banks of IOs are in a channel of a first die. The method includes shifting a first connection between the first IO element and a first core fabric of the first die to second connection between a second IO element and the first core fabric. The second IO element is in the first bank of IOs. The method includes shifting a third connection between a third IO element and a second core fabric of a second die to fourth connection between a fourth IO element and the second core fabric. The third and fourth IO elements are in a third bank of IOs of the second die. The method includes not shifting connections in the second and fourth banks of IOs.
US11336282B2
A device includes a power gating signal generation circuit, a clock interrupt signal generation circuit, and a shift clock generation circuit. The power gating signal generation circuit configured to generate a power gating signal based on a mode entry signal and a mode exit signal to perform a power gating operation. The clock interrupt signal generation circuit configured to generate a clock interrupt signal based on the mode entry signal and the power gating signal to perform a clock interrupt operation. The shift clock generation circuit configured to generate a shift clock signal supplied to an internal circuit based on the power gating signal and the clock interrupt signal.
US11336280B2
A half-bridge control circuit comprises an input terminal, an output terminal for providing a pulsed signal to a half-bridge driver circuit configured to drive two electronic switches connected between two supply terminals, and a feedback terminal for receiving a feedback signal indicative of the instantaneous voltage value at a switching node between the two electronic switches. A selector circuit provides a digital feedback signal. A subtractor generates an error signal by subtracting the digital feedback signal from the reference signal. An integrator generates an integration signal by integrating the value of the error signal. A down-scale circuit generates a reduced resolution integration signal by discarding one or more least significant bits of the integration signal. A sampling circuit generates a sampled integration signal by sampling the reduced resolution integration signal. A pulse generator circuit generates the pulsed signal as a function of the sampled integration signal.
US11336279B2
A device includes a heterojunction device, a unipolar power transistor operatively connected in series with said hetero junction device; an external control terminal for driving said unipolar power transistor and said heterojunction device; and an interface unit having a plurality of interface terminals. A first interface terminal is operatively connected to an active gate region of the heterojunction device and a second interface terminal is operatively connected to said external control terminal. The heterojunction device includes a threshold voltage less than a threshold voltage of the unipolar power transistor, wherein the threshold voltage of the heterojunction device is less than a blocking voltage of the unipolar power transistor.
US11336274B2
The present disclosure mainly provides a clamping circuit, coupled to a first end and a second end of a switching transistor through a first node and a second node, comprising: an RCD circuit, comprising a first resistor and a first capacitor connected in parallel between the second node and a third node, and a diode having a negative electrode coupled to the third node; and a first stabilivolt diode, having a negative electrode coupled to the first node and a positive electrode coupled to a positive electrode of the diode at a fourth node.
US11336268B2
Integrated circuit, comprising at least one ring oscillator including a succession of inverters looped back to form the ring, the at least one oscillator being intended to operate at a desired output frequency and configured so that the inverter transistors operate in or near their temperature inversion zone.
US11336265B2
Several embodiments of electrical circuit devices and systems with clock distortion calibration circuitry are disclosed herein. In one embodiment, an electrical circuit device includes an electrical circuit die having clock distortion calibration circuitry to calibrate a clock signal. The clock distortion calibration circuitry is configured to compare a first duty cycle of a first voltage signal of the clock signal to a second duty cycle of a second voltage signal of the clock signal. Based on the comparison, the clock distortion calibration circuitry is configured to adjust a trim value associated with at least one of the first and the second duty cycles of the first and the second voltage signals, respectively, to calibrate at least one of the first and the second duty cycles and account for duty cycle distortion encountered as the clock signal propagates through a clock tree of the electrical circuit device.
US11336253B2
An amplifier circuit includes a first port, a second port, a reference potential port, and an RF amplifier device having a first terminal electrically coupled to the first port, a second terminal electrically coupled to the second port, and a reference potential terminal electrically coupled to the reference potential port. The RF amplifier device amplifies an RF signal across an RF frequency range that includes a fundamental RF frequency. An impedance matching network is electrically coupled to the first terminal and the first port. The impedance matching network includes a baseband termination circuit that presents low impedance in a baseband frequency region, a fundamental frequency matching circuit that presents a complex conjugate of an intrinsic impedance of the RF amplifier device in the RF frequency range, and a second order harmonic termination circuit that presents low impedance at second order harmonics of frequencies in the fundamental RF frequency range.
US11336252B2
A filter (10) includes two capacitors (C1a and C1b) that are connected in series on a path connecting an input terminal (101a) and an output terminal (102a), an inductor (L2) that is connected in parallel with a series circuit including the two capacitors (C1a and C1b), and a parallel-arm resonator (P1) that is connected between the ground and a node (N) between the two capacitors (C1a and C1b) on the path.
US11336249B2
A multilayer filter may include a plurality of dielectric layers stacked in a Z-direction. A first conductive layer may overlie one of the dielectric layers, and a second conductive layer may overlie another of the dielectric layers and be spaced apart from the first conductive layer in the Z-direction. A first via may be connected with the second conductive layer at a first location. A second via may be connected with the second conductive layer at a second location that is spaced apart in a first direction from the first location. The first conductive layer may overlap the second conductive layer at an overlapping area to form a capacitor. At least a portion of the overlapping area may be located between the first location and the second location in the first direction. The second conductive layer may be free of via connections that intersect the overlapping area.
US11336247B1
According to an embodiment of the disclosure, a series or source feedback is provided to a solid-state power amplifier to achieve improved amplifier output power, good impedance match, and low voltage standing wave ratio (VSWR). In an embodiment, an inductive element is coupled to the source of the power amplifier transistor to serve as a series or source feedback for the transistor. In an embodiment, a high-impedance transmission line such as a microstrip or coplanar waveguide is provided as an inductive element coupled to the source of the transistor. In an embodiment, a series or source feedback is provided to each amplifier in a multistage amplifier circuit.
US11336243B2
A receiver topology for supporting various combinations of interband carrier aggregation (CA) signals, intraband non-contiguous CA and non-CA signals having different combinations of signals aggregated therein.
US11336242B2
A communication circuit, including a first supply modulator configured to provide a first supply voltage; a first power amplifier configured to generate a first output signal by amplifying a first input signal corresponding to a first operation frequency band; a second power amplifier configured to generate a second output signal by amplifying a second input signal corresponding to a second operation frequency band; and a switching circuit configured to selectively provide the first supply voltage from the first supply modulator to the second power amplifier based on a first switching signal according to an operation mode.
US11336226B2
Techniques are described that enables controlling the TNULL characteristic of a self-compensated oscillator by controlling the magnitude and direction of the frequency deviation versus temperature, and thus, compensating the frequency deviation.
US11336221B2
A solar array includes a solar module and a support structure for the solar module. The support structure includes a support member. The solar module is mounted on the support structure such that the solar module is positioned at least partially above the support member. The solar array also includes a wire receiver for securing wires to the solar module or the support member. The wire receiver includes a wire insert slot sized for receiving wires, a wire transition slot connected to the wire insert slot, and a catch adapted to inhibit movement of the wires. The wire insert slot and the wire transition slot are sized and arranged for the wires to be inserted into the wire insert slot and positioned around the catch.
US11336210B2
A vibration type actuator including vibrating elements and a contact element that is brought into contact with each other in a first direction. The vibration of the vibrating elements includes vibration in a first vibration mode in the first direction and vibration in a second vibration mode in a second direction intersecting the first direction. In the vibrating elements, a minimum value of a resonance frequency in the second vibration mode is greater than or equal to a maximum value of a resonance frequency in the first vibration mode, and a ratio of a difference between the maximum value and the minimum value of the resonance frequency in the second vibration mode to the minimum value of the resonance frequency in the second mode is less than or equal to a predetermined value.
US11336207B2
Disclosed is a high-power sliding-mode triboelectric generator including a substrate; a positive electrode formed on the substrate; a positively charged body provided on the positive electrode and formed to be tilted at a predetermined angle from the substrate; a negatively charged body located to be opposite to the positively charged body and formed to be tilted at the same angle as in the positively charged body; a negative electrode provided on the negatively charged body and configured to support the negatively charged body; and at least one spacer formed between the positively charged body and the negatively charged body, is formed of an elastic body, and configured to maintain an interval between the positively charged body and the negatively charged body.
US11336206B2
Methods, non-transitory computer readable mediums, and power conversion systems with a controller configured to provide modulated inverter switching control signals at a first switching frequency in response to an inverter current being greater than a first threshold and less than a second threshold, the second threshold being greater than the first threshold. The controller is further configured to provide the inverter switching control signals at a second switching frequency in response to the inverter current being greater than the second threshold, and to provide the inverter switching control signals at a third switching frequency in response to the inverter current being less than the first threshold, where the second switching frequency is less than the first switching frequency and the third switching frequency is greater than the first switching frequency.
US11336194B1
Disclosed herein is a DC-AC converter, in accordance with some embodiments. Accordingly, the DC-AC converter comprises a transformer, a pulse generator, a pulse modulator, a switching element, and an analog low pass filtering stage. Further, the pulse generator is configured for generating pulses characterized by a pulse frequency. Further, the pulse modulator is configured for generating a pulse density modulated signal based on modulating the pulses using a sine wave signal of a fundamental frequency. Further, the switching element is connected in series with a primary winding of the transformer. Further, the switching element is configured to be switched between an on state and an off state based on the pulse density modulated signal. Further, the analog low pass filtering stage is configured for generating an AC voltage of the fundamental frequency based on attenuating higher frequency components of an unfiltered AC voltage at a secondary winding of the transformer.
US11336192B2
A three-phase power apparatus with bidirectional power conversion applied to charge a battery of an electric vehicle. The three-phase charging apparatus includes an AC-to-DC conversion unit, a first DC bus, a first DC-to-DC conversion unit, a second DC bus, and a second DC-to-DC conversion unit. The first DC bus is coupled to the AC-to-DC conversion unit. The first DC-to-DC conversion unit includes an isolated transformer, a resonant tank, a first bridge arm assembly, and a second bridge arm assembly. The first bridge arm assembly is coupled to the first DC bus and a primary side of the isolated transformer. The second bridge arm assembly is coupled a secondary side of the isolated transformer. The second DC bus is coupled to the second bridge arm assembly. The second DC-to-DC conversion unit is coupled to the second DC bus and the battery.
US11336191B1
A power supply device with low loss includes an input switch circuit, a transformer, a first capacitor, an output stage circuit, and a detection and control circuit. The input switch circuit generates a switching voltage according to an input voltage. The output stage circuit generates an output voltage. The output stage circuit includes a first rectifying switch element and a second rectifying switch element. The detection and control circuit detects a first output current flowing through the first rectifying switch element so as to generate a first control voltage, and it detects a second output current flowing through the second rectifying switch element so as to generate a second control voltage. The first rectifying switch element is selectively closed or opened according to the first control voltage. The second rectifying switch element is selectively closed or opened according to the second control voltage.
US11336187B2
A resonant switching converter can include: a voltage switching circuit configured to receive a first input voltage, and to generate a second input voltage of a resonant branch coupled to the voltage switching circuit; where when the voltage switching circuit is in a first operating state, the second input voltage provided to the resonant branch is less than the first input voltage; and where when the voltage switching circuit is in a second operating state, the input voltage provided to the resonant branch is zero.
US11336178B2
A power converter is disclosed. The power converter includes a Single-Input-Multiple-Output (SIMO) device includes a first transistor connected to an input and a first end of an inductor, a second transistor connected to a second end of the inductor and a first output, and a third transistor connected to the second end of the inductor and a second output. The power converter also includes a controller connected to the SIMO device and is configured to maintain a minimum inductor current through the inductor between charging cycles and to cause the minimum inductor current to transition to a charging inductor current during a charging cycle. The charging inductor current is based on a difference between an output voltage signal and a target voltage signal.
US11336176B1
An internal voltage generation circuit may include an oscillation circuit, a signal generation circuit, and a pumping circuit. The oscillation circuit may generate an oscillation signal. The signal generation circuit may generate first and second pumping driving signals on the basis of the oscillation signal. The pumping circuit may generate a pumping voltage through a pumping operation on the basis of the first and second pumping driving signals.
US11336171B2
The present invention discloses a converter with cold start-up and a cold start-up method for modular power converters that allows converter operation tests to be carried out without a connection to the AC grid. For that purpose, the control module powers the power converter modules, disconnects the power converter from the AC grid, selects a power converter module as the AC-source module and configures a voltage and a frequency for the AC-source module, selects the power for the other power converter modules and sets starting conditions. Previously, the control module is powered by an AC source that can be internal or external, such as an uninterruptible power supply (UPS) or a DC source (photovoltaic field), via a DC-AC transformer.
US11336165B2
A linear motor system has multiple modular track sections joined end-to-end to form a track along which movers may be displaced by the control of magnetic fields generated by coils disposed in each track section. A curved track section is provided that includes a curved portion, an integral straight portion, and a fit spline transition between the curved portion and the straight portion. The integration of the straight portion smooths the transition between the curved and straight areas of the track, and allows for improved performance.
US11336163B2
An apparatus is provided for forming an axial flux permanent magnet synchronous motor. The apparatus includes a stator assembly including a plurality of stator poles spaced about a stator shaft, each comprising a winding. Adjacent pairs of stator poles have a spacing in a circumferential direction approximately equal to or greater than a width of the stator pole. A rotor assembly includes a plurality of rotor poles of alternating magnetic polarity arranged for electrically communicating with the windings of the stator assembly. The ratio of stator poles to rotor poles may be less than 4:6 or, more specifically, less than or equal to about 1:2.
US11336159B2
The manufacturing method of a rotor includes: a step of preparing a plate that is composed of an austenitic material and that has a projected portion and a part with a width in a rotational axis direction smaller than a width of the projected portion in the rotational axis direction; and a step of forming a welded portion across the projected portion of the plate and a rotation transmitting member by emitting an energy beam on at least a part of the projected portion to melt at least a part of the projected portion.
US11336143B2
A stator assembly for use in a motor includes an annular stator and a circuit board. The stator having an annular shape is centered on a central axis extending vertically. The circuit board is above the stator in an axial direction. The stator includes a stator core, an insulator, a conductive wire, and a terminal pin. The stator core includes teeth. The insulator covers at least a portion of the stator core. The conductive wire is wound around the teeth via the insulator to define a coil. The terminal pin extends axially upward from an upper surface of the insulator and is connected to an end portion of the conductive wire. The circuit board includes a solder portion on an upper surface. The solder portion enables electrical connection with the terminal pin and is covered with a coating layer.
US11336140B2
The invention mainly concerns a coiling procedure of a stator for a multiphase electrical rotating machine: the said stator comprising grooves, each intended to take up an uneven number of conductors of a coil, the said coil comprising two systems, each comprising one group of conductors (C1-C3, C1′-C3′) respectively, the said procedure comprises stages of installation of the conductors (C1-C3, C1′-C3′) into the said grooves, repeated in order to form a coil comprising several turns (S1-S9) completed alternately according to a first direction of rotation (K1) and according to a second direction of rotation (K2) opposite the first direction of rotation, with the characteristic that at least two changes of direction of rotation (CH1-CH8) from one turn to the other are carried out in different angular zones.
US11336135B2
Disclosed is a motor rotor structure including a rotor core. A plurality of radial slots each are in the rotor core along a circumferential direction, and a first flux barrier slot is provided between every two adjacent radial slots. Two kinds of permanent magnets having different coercivities mounted in each radial slot. The two kinds of permanent magnets having different coercivities are distributed along a radial direction of the rotor core. The two kinds of permanent magnets having different coercivities are both magnetized along a tangential direction of the rotor core. A second flux barrier slot is provided between the two kinds of permanent magnets having different coercivities.
US11336132B2
An electric machine includes a rotor configured to rotate about an axis of rotation, a stator having a stator core and a plurality of teeth annularly arranged on the stator core about the axis of rotation, a plurality of electromagnetic coils, and a base plate. Each coil of the plurality of electromagnetic coils may be mounted on a separate tooth of the plurality of teeth. The base plate may be located adjacent to the plurality of electromagnetic coils and the stator core. The base plate may have a first side and an opposing second side. The first side may be in thermal contact with the plurality of electromagnetic coils and the stator core. A liquid-coolant channel may be defined on the second side of the base plate such that as the coils and the stator core heats during operation, the base plate is configured to transfer the heat to a liquid coolant in the liquid-coolant channel to dissipate heat from the plurality of electromagnetic coils and the stator core.
US11336129B2
Systems, methods and apparatus for wireless charging are disclosed. A charging device has a charging circuit that includes a charging coil located proximate to a surface of the charging device, a pulse generating circuit, and a controller. The pulse generating circuit may be configured to provide a pulsed signal to the charging circuit, where each pulse in the pulsed signal includes a plurality of cycles of a clock signal that has a frequency greater or less than a nominal resonant frequency of the charging circuit. The controller may be configured to detect a change in resonance of the charging circuit based on a difference in response of the charging circuit to first and second pulses transmitted in the pulsed signal. The controller may be further configured to determine that a chargeable device has been placed in proximity to the charging coil based on the difference in responses.
US11336126B2
A transmitter of a wireless power transfer and data communication system comprising a transmitter system including a transmitter housing, one or more high-power laser sources, a laser controller, one or more low-power laser sources, one or more photodiodes, a beam steering system and lens assembly, and a safety system. High-power and low-power beams are directed to corresponding receivers and transceivers of a transceiver system inside a remote receiver system by the controller and the beam steering system and lens assembly. Low-power beams include optical communication to the transceiver system. The photodiodes of the transmitter system receive optical communication from the transceiver system. Low-power beams are co-propagated with and in close proximity to high-power beams substantially along an entire distance between the transmitter housing and the receiver system. The safety system instructs the controller to reduce the high-power sources in response to detected events.
US11336125B2
Methods and devices addressing power tracking of transmission systems using antenna arrays are disclosed. The disclosed teachings may be implemented on a channel element to channel element basis, are adaptive and can be implemented on short time durations such as time slots. Power efficiency can be improved when applying the described methods to the design of systems with antenna arrays.
US11336124B2
A method of transmitting a signal by a wireless power transmitter in a wireless charging system, wireless power transmitter, and a wireless power receiver are provided. The method includes receiving, from a wireless power transmitter, a first beacon power for a first duration time in every first period; receiving, from the wireless power transmitter, a second beacon power for a second duration time in every second period; if the wireless power receiver determines that an extension of the second beacon power is required, generating load changes while receiving the second beacon power for the second duration time; in response to the generated load changes, continually receiving, from the wireless power transmitter, the second beacon power until a predetermined third duration time, wherein the predetermined third duration time is determined before the second beacon power is transmitted by the wireless power transmitter; and transmitting an advertisement signal to the wireless power transmitter while receiving the second beacon power for the predetermined third duration time.
US11336113B2
An electric power system is disclosed herein. The electric power system may manage and store electric power and provide uninterrupted electric power, derived from a plurality of electric power sources, to an electric load. The electric power system may contain an energy storage unit and generator assembly. The electric power system may connect to a power grid and renewable energy sources, and may charge the energy storage unit using the power grid, renewable energy sources, and/or generator assembly. The electric power system may be configured to determine load power usage and environmental factors to automatically and continuously modify a charging protocol to, for example, provide high efficiency and/or self-sufficiency from the power grid. The electric power system may operate entirely off-grid and may provide electricity to the load without interruption to power.
US11336110B2
A rechargeable battery using a solution of an aluminum salt as an electrolyte is disclosed, as well as methods of making the battery and methods of using the battery.
US11336109B2
A dual port battery charging system comprises a charger, a microcontroller, a first switching unit, a second switching unit, a first charging interface and a second charging interface, wherein the microcontroller is coupled with the first switching unit, the second switching unit, the first charging interface and the second charging interface to detect a voltage and a current of a first battery pack or a second battery pack, and the microcontroller can control the first switching unit and the second switching unit to charge the first battery pack and the second battery pack separately or alternately.
US11336107B2
[Object] To achieve both prevention of overcharging of the battery and convenience of the user.
[Solution] An information processing device includes: a charged capacity detection unit configured to detect a charged capacity of a battery; a charging control unit configured to control a charging circuit; and a specification unit configured to specify when discharge of the battery starts. The charging control unit performs charging suppression control on the charging circuit such that the battery is charged to a preparatorily charged capacity that is lower than a fully charged capacity of the battery, on the basis of the charged capacity detected by the charged capacity detection unit, the charging of the battery stops when the charged capacity of the battery reaches the preparatorily charged capacity, and the charging of the battery restarts from the preparatorily charged capacity before discharge of the battery starts.
US11336106B2
A charging system includes: an input voltage supply circuit; a control circuit coupled to the input voltage supply circuit, configured to control the input voltage supply circuit to generate an input voltage according to a battery voltage of a target battery; and a charging circuit, coupled to the control circuit, configured to receive the input voltage and to provide a charging current to charge the target battery. The input voltage is generated according to a function that takes the battery voltage as a parameter. The input voltage is positively correlated with the battery voltage, and is greater than the battery voltage.
US11336105B2
A multi-battery charging and discharging device including a power management integrated circuit (PMIC) module, at least two rechargeable batteries, and a plurality of first field-effect transistors. Each rechargeable battery is connected to a pulse width modulation (PWM) power module of the PMIC module through a field-effect switching transistor, terminals for connecting field-effect switching transistors and the PWM power module are separated from each other. Each of the first field-effect transistors is provided in a connection path between each rechargeable battery and a load. The first field-effect transistor is used to control the connection path between the rechargeable battery and the load to be turned on or turned off.
US11336102B2
The present disclosure provides a battery supply circuit, a device to be charged, and a charging control method. The battery supply circuit includes a first cell, a second cell, a switch, a first switching unit and a second switching unit. A first end of the second cell is coupled to a first end of the second switching unit, and a second end of the second cell is coupled to a first end of the switch, a second end of the second switching unit is coupled to a second end of the switch; a first end of the first cell is coupled to the second end of the switch, a second end of the first cell is coupled to a first end of the first switching unit, and a second end of the first switching unit is coupled to the first end of the switch.
US11336101B2
A system for use with a direct current fast-charging (DCFC) station includes a controller and battery system. The battery system includes first and second battery packs, and first, second, and third switches. The switches have ON/OFF conductive states commanded by the controller to connect the battery packs in a parallel-connected (P-connected) or series-connected (S-connected) configuration. An electric powertrain with one or more electric machines is powered via the battery system. First and second charge ports of the system are connectable to the station via a corresponding charging cable. The first charge port receives a low or high charging voltage from the station. The second charge port receives a low charging voltage. When the station can supply the high charging voltage to the first charge port, the controller establishes the S-connected configuration via the switches, and thereafter charges the battery system solely via the first charge port.
US11336091B2
Provided are an energy storage power supply, a parallel control device for energy storage power supplies and a parallel control method for energy storage power supplies. The energy storage power supply includes a battery module; an inverter module electrically connected to the battery module; an output module electrically connected to the inverter module; an detection module electrically connected to the output module; an communication module communicated with another energy storage power supply; an switching module electrically connected to the inverter module or the output module; and a processor module electrically connected to the detection module, the communication module and the switching module, and is configured to control, according to the power of a load detected by the detection module, the switching module to be electrically connected to the inverter module or the output module.
US11336088B2
Provided is a transient voltage suppression device including a power supply terminal, a ground terminal, a Zener diode, a diode string, and an isolation device. The Zener diode is coupled between the power supply terminal and the ground terminal, and a node is between the Zener diode and the power supply terminal. The diode string has a first terminal, a second terminal, and an input/output (I/O) terminal. The second terminal is coupled to the ground terminal. The isolation device is coupled between the node and the first terminal. When an abnormal current flows through the isolation device and an energy of the abnormal current per unit time exceeds a preset value of the isolation device, the isolation device blocks a path of the abnormal current.
US11336085B2
An under-voltage lockout (UVLO) circuit includes an automatic UVLO threshold configuration. The UVLO circuit may include an over-voltage protection circuit that receives power from a power source, a peak detector that detects a peak voltage output for the power source, a voltage threshold generator that sets a UVLO threshold based on the peak voltage output, and a comparator that compares an instantaneous voltage with the UVLO threshold and configures an operating mode of a device based on the comparison.
US11336080B1
Embodiments of a slotted grommet configured to manage a cable in an electrical cavity are provided. The slotted grommet includes a body structure having a first surface, a second surface opposite to the first surface, and a peripheral surface extending between the first and second surfaces. A first slot is formed in the first surface and extends through the body structure towards the second surface. The first slot defines a chamber having sidewalls in the body structure configured to hold a loop of the cable. The first slot has a first width that is less than a cross-sectional dimension of the cable such that the cable is pinched within the chamber between the first sidewalls to prevent vibration-related chafing of the cable.
US11336078B2
A semiconductor laser diode is specified, the semiconductor laser diode includes a semiconductor layer sequence having an active layer which has a main extension plane and which, in operation, is adapted to generate light in an active region and to emit light via a light-outcoupling surface, the active region extending from a rear surface opposite the light-outcoupling surface to the light-outcoupling surface along a longitudinal direction in the main extension plane, the semiconductor layer sequence having a surface region on which a first cladding layer is applied in direct contact, the first cladding layer having a transparent material from a material system different from the semiconductor layer sequence, and the first cladding layer being structured and having a first structure.
US11336073B2
Disclosed herein is a method comprising injecting light of a first wavelength λ1 into a wavelength division multiplexer; injecting light of a second wavelength λ2 into the wavelength division multiplexer; combining the light of the first wavelength λ1 and the light of the second wavelength λ2 in the wavelength division multiplexer to produce light of a third wavelength λ3; and reflecting the light of the third wavelength λ3 in a dual-Brillouin peak optical fiber that is in communication with the wavelength divisional multiplexer; wherein the dual-Brillouin peak optical fiber has at least two Brillouin peaks, such that an amplitude A1 of at least one of said Brillouin peaks is within 50% to 150% of an amplitude A2 of another Brillouin peak 0.5A2≤A1≤1.5A2; wherein the dual-Brillouin peak optical fiber generates a Brillouin dynamic grating that reflects an improved back-reflected Brillouin signal of the combined light.
US11336070B2
A carbon dioxide gas-discharge slab-laser is assembled in a laser-housing. The laser-housing is formed from a hollow extrusion. An interior surface of the extrusion provides a ground electrode of the laser. Another live electrode is located within the extrusion, electrically insulated from and parallel to the ground electrode, forming a discharge-gap of the slab-laser. The electrodes are spaced apart by parallel ceramic strips. Neither the extrusion, nor the live electrode, include fluid coolant channels. The laser-housing is cooled by fluid-cooled plates attached to the outside thereof.
US11336061B2
A switch assembly includes a switch and a connector. The switch and the connector are configured to interlock, wherein the switch includes a connection extending at least partially along a center axis of the switch, and the connection is configured to receive at least a part of the connector. The connection may include at least one slot and at least one wedge-shaped groove which is extending from the at least one slot and tapered in a direction of the center axis. The connector may include at least one corresponding wedge-shaped protrusion. The at least one corresponding wedge-shaped protrusion may include a resilient contact blade which can interlock with the at least one wedge-shaped groove.
US11336056B2
A connector device comprises a connector and a mating connector. Under a mated state where the connector and the mating connector are mated with each other, the mating connector is positioned forward of the connector in a front-rear direction. The connector comprises at least one supporting portion, at least one lock portion and a receiving portion. The mating connector has at least one mating lock portion and an abutment portion. At least one of the lock portion and the mating lock portion has an intersecting surface which intersects with both the front-rear direction and a perpendicular direction. Under the mated state, the abutment portion is positioned forward beyond the receiving portion in the front-rear direction and is brought into abutment against the receiving portion by a rearward force so that a rearward movement of the abutment portion beyond the receiving portion is regulated by the receiving portion.
US11336044B2
A terminal includes a connecting portion to be electrically connected to a mating terminal by being inserted into the mating terminal. The connecting portion has a sliding region configured to slide on the mating terminal and a contact region configured to contact the mating terminal successively from a tip side. An outermost surface in the sliding region includes a copper-tin alloy layer containing copper and tin. An outermost surface in the contact region includes a tin layer containing tin as a main component. A Vickers hardness of the copper-tin alloy layer is higher than a Vickers hardness of the tin layer.
US11336042B2
A connector includes a flat-plate housing made of insulating resin and including a first positioning hole and a second positioning hole, a plurality of contacts held on the housing, and a first hold-down and a second hold-down made of metal and disposed to correspond to a first positioning hole and a second positioning hole, respectively. The housing includes a CPU board opposed surface to be opposed to a CPU board. The first hold-down includes a reinforcing plate part to cover the CPU board opposed surface around the corresponding first positioning hole. The second hold-down includes a reinforcing plate part to cover the CPU board opposed surface around the corresponding second positioning hole.
US11336040B2
A conductive terminal electrically connects a conductor of a conductive wire to a circuit board. The conductive terminal includes a body, a clamping portion having a pair of clamping arms, and a solder portion having a pair of solder lugs. The body has an opening through which the conductive wire is inserted and a passage communicating with the opening, the passage receiving the conductive wire and extending perpendicular to a surface of the circuit board. The pair of clamping arms extend from the opening towards the circuit board and obliquely towards each other so as to clamp the conductor of the conductive wire inserted through the opening. The solder portion has a pair of solder lugs extending perpendicular to a lengthwise direction of the passage and soldered to a pair of solder pads on the circuit board.
US11336038B2
A connector suitable for being mounted on a coaxial cable comprising at least one metal braid layer surrounding inner parts of the cable and an outer insulating layer surrounding said at least one metal braid layer and a silicone sleeve arranged around the outer insulating layer wherein the connector comprises a ferrule to be arranged in electrical contact with said at least one metal braid layer, wherein said outer insulating layer of the cable is arranged to be stripped away for the length of said electrical contact, a base arranged cylindrically around said ferrule, and a collar arranged at least partially within said base and comprising a body configurable around the ferrule; wherein the body of the collar has a first outer diameter substantially the same as the diameter of the outer insulating layer of the coaxial cable; and the silicone sleeve is arranged, upon mounting the coaxial cable to the connector, between the base and the body of the collar for applying a pressure force to said at least one metal braid layer of the coaxial cable guided to an outer surface of the collar.
US11336026B2
A radio frequency (RF) system includes an RF integrated circuit (IC) die, and an antenna coupled to the RF IC die. The RF system further includes a reflector layer over the RF IC die, the reflector layer extending over at least a portion of the antenna, a combination of the antenna and the reflector layer having a radiation pattern that comprises a main lobe in a first direction parallel to a top surface of the reflector layer.
US11336025B2
An antenna arrangement is disclosed, comprising a first body comprising a communications device including an antenna for transmitting and/or receiving signals via the antenna, and a second body comprising a conductive parasitic element for electromagnetic coupling with the antenna. The first body is physically separate from, or is removably attachable from, the second body. An associated method of transmitting and/or receiving signals is further disclosed.
US11336024B2
A reflection reducing apparatus includes a dielectric base plane (30), a first patch group, a second patch group, and a ground plate (40). A plurality of first conductive patches (10) each resonate in a first direction (α) and a second direction (β) which are different in resonant length from each other. A plurality of second conductive patches include a first direction-oriented patch (20a) and a second direction-oriented patch (20b) which are different in resonant length from each other. The second conductive patches are arranged along an outer periphery of the first patch group at an interval away from the first patch group.
US11336017B2
An antenna structure associated with a wireless communication device comprised of a plurality of structures configured to enable structural, functional or cosmetic functions associated with the device, is proposed in this disclosure. The antenna structure comprises a first plate comprised of a first set of structures of the plurality of structures of the device and a second, different, plate comprised of a second set of structures of the plurality of structures of the device. The antenna structure further comprises an excitation component coupled between the first plate and the second plate. In some embodiments, the first plate, the second plate and at least a part of the excitation component are configured to form a tank circuit, thereby enabling the antenna structure to radiate at a predefined radiation frequency comprising a resonant frequency associated with the tank circuit.
US11336015B2
Disclosed herein are antenna boards, antenna modules, and communication devices. For example, in some embodiments, an antenna board may include: a substrate including an antenna feed structure; an antenna patch, wherein the antenna patch is a millimeter wave antenna patch; and an air cavity between the antenna patch and the substrate.
US11336011B2
A system includes a distributed ledger storing one or more smart contracts; one or more 5G small cells, each having one or more antennas mounted on a housing, each small cell sending packets of data trackable with the distributed ledger; and a processor to control a directionality of the antennas in communication with a predetermined target using 5G protocols.
US11336008B2
In a transmitting-side control apparatus (30), a transmission control unit (32) controls a radiator (11) to transmit an OAM known signal formed by one common OAM transmission mode at each of transmitting-side relative position candidates. An acquisition unit (33) acquires a feedback signal including information about a use transmitting-side relative position based on a reception strength of the OAM known signal transmitted under the control of the transmission control unit (32). An adjustment unit (34) adjusts a relative position between the radiator (11) and a focal point of a reflecting mirror (12) to the use transmitting-side relative position indicated by the information included in the feedback signal.
US11336007B1
A system of antennas, each having disparity operating frequencies, are incorporated into the same aircraft body panels. HF antennas define loops with large internal areas; additional higher frequency antennas are disposed within that large internal area. The higher frequency antennas are sufficiently different so as to prevent coupling. Antennas operating in the same frequency range, disposed on different parallel surfaces are operated in concert as a steerable array.
US11336003B2
A structure for wireless communication having a plurality of conductor layers, an insulator layer separating each of the conductor layers, and at least one connector connecting two of the conductor layers wherein an electrical resistance is reduced when an electrical signal is induced in the resonator at a predetermined frequency. The structure is capable of transmitting or receiving electrical energy and/or data at various near and far field magnetic coupling frequencies.
US11335994B2
An information handling system (IHS) may include a configuration sensor for sensing a physical configuration of the IHS, a first proximity sensor probe for sensing whether a first biological entity element is proximate to a first antenna, a second proximity sensor probe for sensing whether a second biological entity element is proximate to a second antenna, and a third proximity sensor probe for sensing whether a third biological entity element is proximate to a third antenna. The IHS is adapted to reconfigure use of at least two of the first antenna, the second antenna, and the third antenna in response to the sensing of at least one of the first proximity sensor probe, the second proximity sensor probe, and the third proximity sensor.
US11335988B2
A mechanical means for deploying one of two or more feed sources within a test range is presented. The feed source selected for testing is properly positioned for use within the range by rotating one of two or more arms to an upright and locked position. An arm may further include a rotatable antenna wheel with two or more feed sources thereon whereby a selected feed source is rotated into position via the antenna wheel. The antenna wheel includes a center body, feed sources attached to the center body and aligned along a rotational plane, and a shroud disposed about the center body and feed sources. The antenna wheel may include a cooling system for managing heat generated by the feed sources and electronics therefore. In preferred embodiments, the feed source changer is mounted within the range so that a selected feed source communicates an emitted beam onto a reflector which is redirected as a reflected beam toward a device under test. Concealment panel(s) may be positioned adjacent to the feed source changer to minimize electromagnetic reflections therefrom.
US11335985B2
A tunable microwave system includes at least two elements, each element being chosen from a propagating guide, an evanescent guide, a resonator, and at least one coupling device arranged between the two elements and configured to couple the two elements to each other, the coupling device having a holder having an aperture and having at least one elongate element the shape of which is elongate in a polarization direction contained in a plane of the aperture, the elongate element being securely fastened to the perimeter of the aperture at at least one end, the coupling device being configured to be rotatable about an axis substantially perpendicular to the plane of the aperture so as to modify a value of the polarization direction and so that the coupling between the two elements is dependent on the value of the polarization direction.
US11335983B2
A liquid reserve battery including: a collapsible storage unit having a liquid electrolyte stored therein; a battery cell in communication with an outlet of the collapsible storage unit, the battery cell having gaps dispersed therein; a first pyrotechnic material partially disposed adjacent the collapsible storage unit such that initiation of the first pyrotechnic material provides pressure to collapse the collapsible storage unit to heat and force the liquid electrolyte through the outlet and into the gaps; and a tube disposed in the battery cell, wherein second pyrotechnic material is disposed in the tube, the tube being one of formed of an electrically non-conductive material or covered with an electrically non-conductive material.
US11335977B1
Batteries according to embodiments of the present technology may include a first battery cell including a first current collector. The batteries may include a second battery cell including a second current collector. The second battery cell may be vertically aligned with the first battery cell, and the second current collector may be positioned adjacent the first current collector. The first battery cell and the second battery cell may be electrically coupled together so the first battery cell and the second battery cell transfer current through the cells between the first current collector and the second current collector. The batteries may also include a patterned coupling material disposed between the first battery cell and the second battery cell and joining the first current collector with the second current collector.
US11335973B2
A layered double hydroxide (LDH) separator capable of more effectively restraining short circuiting caused by zinc dendrites. The LDH separator for secondary zinc batteries includes a porous substrate made of a polymer material and a LDH plugging pores in the porous substrate. The LDH separator has a dendrite buffer layer therein, the dendrite buffer layer being at least one selected from the group consisting of: (i) a pore-rich internal porous layer in the porous substrate, the internal porous layer being free from the LDH or deficient in the LDH; (ii) a releasable interfacial layer; which is provided by two adjacent layers constituting part of the LDH separator in releasable contact with each other; and (iii) an internal gap layer free from the LDH and the porous substrate, which is provided by two adjacent layers constituting part of the LDH separator formed apart from each other.
US11335970B2
A battery pack includes a pack case configured to accommodate a cell module assembly in an inner space thereof and having an opening formed at one side, and a pack cover having a degassing port communicating with the inner space and configured to cover the opening of the pack case. The cell module assembly includes a cell fixing frame having an upper plate and a lower plate respectively disposed at an upper portion and a lower portion of the cell stack and in surface contact with an upper wall and a lower wall of the pack case. At least one of the upper plate and the lower plate includes at least one gas moving route formed by concavely depressing one surface in contact with the upper wall or the lower wall of the pack case along a path toward the degassing port, and at least one hole.
US11335965B2
A heating device for a prismatic battery cell of a high-voltage battery of a motor vehicle includes two sheet-shaped heating elements to be arranged on two opposite lateral outer sides of a cell housing of the battery cell, and two connecting elements to be arranged on a housing cover of the cell housing. The connecting elements are electrically connected to terminals of the two heating elements. The connecting elements are flexibly formed, at least in certain regions, and as a result the heating elements are connected in a hinge-like manner. The heating device can be arranged by arranging the first heating element on the first lateral outer side of the cell housing, swinging the second heating element over the housing cover, and arranging the second heating element on the second lateral outer side on the cell housing.
US11335964B2
A cold plate for a battery module comprising a plurality of cells that produces heat as charging and discharging is disclosed. The cold plate includes a plurality of first fins distributed in a first subarea of the cold plate; and a plurality of second fins distributed in a second subarea of the cold plate; wherein a second fin coverage of the plurality of second fins distributed in the second subarea is smaller than a first fin coverage of the plurality of first fins distributed in the first subarea when an amount of heat absorption of the second subarea from the plurality of cells is greater than an amount of heat absorption of the first subarea from the plurality of cells.
US11335941B2
The present disclosure relates to an apparatus and a method for manufacturing a battery cell, and more particularly, to an apparatus and a method for manufacturing a battery cell, wherein a pressing jig provided with a semi-elliptical pressing part presses the battery cell to remove air bubbles from the battery cell.
US11335922B2
An energy conversion system includes an energy converter, a cold generator, and a liquid water obtainer. The energy converter is configured to convert energy of a source from one form to another form and generate heat and water vapor. The cold generator is configured to generate cold using the heat generated by the energy converter. The liquid water obtainer is configured to condense the water vapor using the cold to obtain liquid water. Accordingly, the water vapor generated from the energy converter can be cooled efficiently. Therefore, efficiency in obtaining the liquid water can be improved compared with a case where the water vapor is cooled by open air.
US11335919B2
An electrochemical cell stack comprises a plurality of electrochemical cell units, each comprising a cathode, an anode, and an electrolyte, and also comprises a plurality of interconnects. An interconnect is disposed between adjacent electrochemical cell units and defines a longitudinal channel having circumferential corrugations defined therearound. A fuel channel is defined between each anode and a respective adjacent interconnect, the fuel channel having fuel inlet and outlet. An oxidant channel is defined between each cathode and a respective adjacent interconnect, the oxidant channel having an oxidant inlet and outlet. The plurality of electrochemical cell units and interconnects include a first electrochemical cell unit, a first interconnect adjacent the first electrochemical cell unit, a second electrochemical cell unit adjacent the first interconnect, and a second interconnect adjacent the second electrochemical cell unit. The second interconnect is rotationally offset from the first interconnect about a longitudinal axis of the fuel cell stack.
US11335918B2
A fuel electrode incorporates a first and second corrugated portion that are attached to each other at offset angles respect to their corrugation axis and therefore reinforce each other. A first corrugated portion may extend orthogonally with respect to a second corrugated portion. The first and second corrugated portions may be formed from metal wire and may therefore have a very high volumetric void fraction and a high surface area to volume ratio (sa/vol). In addition, the strands of the wire may be selected to enable high conductivity to the current collectors while maximizing the sa/vol. In addition, the shape of the corrugation, including the period distance, amplitude and geometry may be selected with respect to the stiffness requirements and electrochemical cell application factors. The first and second corrugated portions may be calendared or crushed to reduce thickness of the fuel electrode.
US11335917B2
An apparatus includes a thermal battery, which includes a housing and one or more battery cells within the housing. Each battery cell includes an anode, a cathode, and an electrolyte. The electrolyte in each battery cell is configured to be in a solid state when the battery cell is inactive. The apparatus also includes a phase change material around at least part of the housing. The phase change material is configured to conduct external heat into the housing in order to melt the electrolyte in each battery cell and activate the battery cell. The phase change material is also configured to change phase in order to reduce conduction of the external heat into the housing.
US11335914B2
A method of making an interconnect for a solid oxide fuel cell stack includes providing an iron rich material containing at least 25 wt. % iron into channels of a mold, providing a powder containing 4-6 wt. % Fe, 0-1 wt. % Y and balance Cr into the mold over the iron rich material containing at least 25 wt. % iron, compacting the iron rich material containing at least 25 wt. % iron and the powder comprising 4-6 wt. % Fe, 0-1 wt. % Y and balance Cr in the mold to form the interconnect, and sintering the interconnect to form a sintered interconnect having iron rich regions having an iron concentration greater than 10% in ribs of the interconnect.
US11335907B2
A powderous positive electrode material for a lithium secondary battery has the general formula Li1+x[Ni1−a−b−cMaM′bM″c]1−xO2−z. M is one or more elements of the group Mn, Zr and Ti. M′ is one or more elements of the group Al, B and Co. M″ is a dopant different from M and M′, and x, a, b and c are expressed in mol with −0.02≤x≤0.02, 0≤c≤0.05, 0.10≤(a+b)≤0.65 and 0≤z≤0.05. The material has an unconstrained cumulative volume particle size distribution value (Γ0(D10P=0)), a cumulative volume particle size distribution value after having been pressed at a pressure of 200 MPa (ΓP(D10P=200)) and a cumulative volume particle size distribution value after having been pressed at a pressure of 300 MPa (ΓP(D10P=300)). When ΓP(D10P=200) is compared to Γ0(D10P=0), the relative increase in value is less than 100%. When ΓP(D10P=300) is compared to Γ0(D10P=0), the relative increase in value is less than 120%.
US11335900B2
A composite nanosheet for the cathode of a lithium-sulfur battery, a preparation method thereof, and an electrode and a battery having the same. The composite nanosheet includes carbon nanotubes which are closely accumulated in a two-dimensional plane and are combined together by carbon derived from nanocellulose. Transition metal compound nanoparticles which are uniformly distributed in the nanosheet composite and are fixed by the carbon derived from nanocellulose. Sulfur adsorbed on the surface of the transition metal compound nanoparticles. The composite organically combines and exerts the respective advantages of porous carbon, carbon nanotubes and nano metal oxides/sulfide by designing and constructing the structure of the cathode material.
US11335899B2
A catholyte-like material including a cathode material and an interfacial additive layer for providing a lithium ion energy storage device having low impedance is disclosed. The interfacial additive layer, which is composed of vapor deposited iodine, is present between the cathode material and an electrolyte layer of the device. The presence of such an interfacial additive layer increases the ion and electron mobile dependent performances at the cathode material interface due to significant decrease in the resistance/impedance that is observed at the respective interface as well as the impedance observed in the bulk of the device. The catholyte-like material of the present application can be used to provide a lithium ion energy storage device having high charge/discharge rates and/or high capacity.
US11335888B2
Disclosed is an electroluminescent display device comprising an a substrate including a display area and a non-display area, an emission device in the display area on the substrate, an encapsulation layer extending from the display area to the non-display area, wherein the encapsulation layer is provided on the emission device, a plurality of pad electrodes in the non-display area on the substrate, and a protection layer provided in the area between each of the plurality of pad electrodes, and configured to protect an insulating layer disposed there below, wherein the encapsulation layer is provided with an opening area configured to expose at least a portion in each of the plurality of pad electrodes and at least a portion of the protection layer.
US11335887B2
A display device according to the present invention includes a display region arranged with a plurality of pixels, and a sealing layer covering the display region, wherein the sealing layer includes an insulation layer having a density pattern, the density pattern is a pattern including a low density region and a high density region, the low density region has the insulation layer with a lower density than an average density within the display region of the insulation layer, and the high density region has the insulation layer with a higher density than an average density within the display region of the insulation layer.
US11335885B2
The display device includes a substrate including a first resin layer, a second resin layer overlapping the first resin layer, and a first inorganic insulating layer between the first resin layer and the second resin layer, and having flexibility, a display region provided on the substrate, a terminal region arranged outside the display region on the substrate, and a bending region arranged between the display region and the terminal region. A thickness of the second resin layer is larger than a thickness of the first resin layer. The substrate includes a first region and a second region. The first resin layer, the first inorganic insulating layer, and the second resin layer are laminated in the first region. The first resin layer and the second resin layer are laminated in the second region and the first inorganic insulating layer is not laminated in the second region.
US11335881B2
A display panel is provided. A side surface of an interlayer insulating layer away from the substrate is partially recessed to a substrate so as to form a first groove. A crack preventing member is filled in the first groove and is connected to the substrate, so a connection of the organic layer to the organic layer is achieved, thereby increasing a bending resistance of the display panel and reducing the risk of film peeling. In addition, a side surface of the interlayer insulating layer disposed between the first groove and the banks away from the substrate is partially recessed to form a second groove, and the first inorganic packaging layer is filled in the second groove. An inorganic layer of the packaging layer is connected to an inorganic layer of an array substrate, thereby increasing a bending resistance of the display panel and reducing the risk of film peeling.
US11335870B2
Provided is a method for preparing a display substrate. The display substrate includes multiple pixel island regions, empty regions and connection bridge regions. The preparation method includes: forming first grooves corresponding to the pixel island regions and second grooves corresponding to the connection bridge regions on a side of a hard underlay substrate; preparing the display substrate on a side of the underlay substrate where the first grooves and the second grooves are formed, wherein the pixel island regions are located in regions where the first grooves are located, the connection bridge regions are located in regions where the second grooves are located, and the empty regions are located in regions other than the first grooves and the second grooves; and separating the underlay substrate from the display substrate to obtain the display substrate.
US11335853B2
A method of manufacturing an OTS device of the invention is a method of manufacturing OTS device including a first conductor, an OTS portion made of chalcogenide, and a second conductor which are layered in order and disposed on an insulating substrate. The manufacturing method includes: a step D of forming a resist so as to coat part of an upper surface of the second conductor; a step E of dry etching a region which is not coated with the resist; and a step F of ashing the resist. In the step E, the second conductor, all of the OTS portion, and an upper portion of the first conductor are removed by an etching treatment once in a depth direction of the region.
US11335838B2
A light emitting device including a contact layer, a blocking layer over the contact layer, a protection layer adjacent the blocking layer, a light emitter over the blocking layer, and an electrode layer coupled to the light emitter. The electrode layer overlaps the blocking layer and protection layer, and the blocking layer has an electrical conductivity that substantially blocks flow of current from the light emitter in a direction towards the contact layer. In addition, the protection layer may be conductive to allow current to flow to the light emitter or non-conductive to block current from flowing from the light emitter towards the contact layer.
US11335831B2
An optical device case (100A) of an embodiment includes: a light-transmitting window member (20A); and a housing (10) which has a space for accommodating a light-receiving element and/or a light-emitting element (OE), wherein the window member (20A) includes a light-transmitting member (22), a polymer film (50) provided on an outer surface of the light-transmitting member (22), the polymer film (50) having a moth-eye structure at its surface, a contact angle of the surface with respect to water being not less than 140°, and a resistance heater (24) provided on an inner surface of the light-transmitting member (22).
US11335822B2
A multijunction solar cell includes a base substrate comprising a Group IV semiconductor and a dopant of a first carrier type. A patterned emitter is formed at a first surface of the base substrate. The patterned emitter comprises a plurality of well regions doped with a dopant of a second carrier type in the Group IV semiconductor. The base substrate including the patterned emitter form a first solar subcell. The multijunction solar cell further comprises an upper structure comprising one or more additional solar subcells over the first solar subcell. Methods of making a multijunction solar cell are also described.
US11335821B2
Low noise silicon-germanium (SiGe) image sensor. In one embodiment, an image sensor includes a plurality of pixels arranged in rows and columns of a pixel array disposed in a semiconductor substrate. The photodiodes of an individual pixel are configured to receive an incoming light through an illuminated surface of the semiconductor substrate. The semiconductor substrate includes a first layer of semiconductor material having silicon (Si); and a second layer of semiconductor material having silicon germanium (Si1-xGex). A concentration x of Ge changes gradually through at least a portion of thickness of the second layer. Each photodiode includes a first doped region extending through the first layer of semiconductor material and the second layer of semiconductor material; and a second doped region extending through the first layer of semiconductor material and the second layer of semiconductor material.
US11335812B2
A novel semiconductor device is provided. A component extending in a first direction, and a first conductor and a second conductor extending in a second direction are provided. The component includes a third conductor, a first insulator, a first semiconductor, and a second insulator. In a first intersection portion of the component and the first conductor, the first insulator, the first semiconductor, the second insulator, a second semiconductor, and a third insulator are provided concentrically. In a second intersection portion of the component and the second conductor, the first insulator, the first semiconductor, the second insulator, a fourth conductor, and a fourth insulator are provided concentrically around the third conductor.
US11335810B2
A transistor includes a substrate having a first surface and a second surface opposite the first surface, a drift region having a doped region on the first surface of the substrate and a graded doping region on the doped region, a semiconductor fin protruding from the graded doping region and comprising a metal compound layer at an upper portion of the semiconductor fin, a source metal contact on the metal compound layer, a gate layer having a bottom portion directly contacting the graded doping region; and a drain metal contact on the second surface of the substrate.
US11335800B2
A semiconductor device is disclosed. The semiconductor device includes a substrate, an epitaxial layer on the substrate, a semiconductor interlayer on top of the epitaxial layer, a gate conductor above the semiconductor interlayer, a gate insulator on the bottom and sides of the gate conductor and contacting the top surface of the semiconductor interlayer, a source region extending into the epitaxial layer, and a drain region extending into the epitaxial layer. The semiconductor device also includes a first polarization layer on the semiconductor interlayer between the source region and the gate conductor and a second polarization layer on the semiconductor interlayer between the drain region and the gate conductor.
US11335797B2
A semiconductor device is provided. The semiconductor device includes a channel layer disposed on a substrate, a barrier layer disposed on the channel layer, and a nitride layer disposed on the barrier layer. The semiconductor device also includes a compound semiconductor layer that includes an upper portion and a lower portion, wherein the lower portion penetrates through the nitride layer and a portion of the barrier layer. The semiconductor device also includes a spacer layer conformally disposed on a portion of the barrier layer and extending onto the nitride layer. The semiconductor device further includes a gate electrode disposed on the compound semiconductor layer, and a pair of source/drain electrodes disposed on opposite sides of the gate electrode. The pair of source/drain electrodes extends through the spacer layer, the nitride layer, and at least a portion of the barrier layer.
US11335780B2
An epitaxial structure includes a substrate, a buffer layer, a back diffusion barrier layer, a channel layer formed on the back diffusion barrier layer, and a barrier layer formed on the channel layer. The buffer layer is formed on the substrate. The back diffusion barrier layer is formed on the buffer layer. The chemical composition of the back diffusion barrier layer is AlxInyGa1-x-yN, wherein 0≤x≤1 and 0≤y≤1. The lattice constant of the back diffusion barrier layer is between 2.9 Å and 3.5 Å. The back diffusion barrier layer is composed of a plurality of regions in the thickness direction, and the aluminum (Al) content and the indium (In) content of the back diffusion barrier layer are changed stepwise or gradually changed stepwise along the thickness direction. The back diffusion barrier layer further includes carbon, and the carbon concentration is changed stepwise or gradually changed stepwise along the thickness direction.
US11335775B2
Some embodiments include a transistor having an active region containing semiconductor material. The semiconductor material includes at least one element selected from Group 13 of the periodic table in combination with at least one element selected from Group 16 of the periodic table. The active region has a first region, a third region offset from the first region, and a second region between the first and third regions. A gating structure is operatively adjacent to the second region. A first carrier-concentration-gradient is within the first region, and a second carrier-concentration-gradient is within the third region. Some embodiments include methods of forming integrated assemblies.
US11335771B2
A semiconductor device includes first and second electrodes, a semiconductor part therebetween; first and second control electrodes each in a trench at the frontside of the semiconductor part. The semiconductor part includes first to sixth layers. The first and third layers are of a first conductivity type. Other layers are of a second conductivity type. The first layer extends between the first electrode at the backside and the second electrode at the frontside. The second layer is provided between the first layer and the second electrode. The third and fourth layers each are selectively provided between the second layer and the second electrode. The fifth layer is provided between the first layer and the first electrode. The sixth layer is provided between the first layer and the second control electrode. The sixth layer extends along an insulating film between the semiconductor part and the second control electrode.
US11335751B2
A display device includes: a substrate; a data line disposed on the substrate; an another data line disposed on the substrate and adjacent to the data line; a first light emitting diode including a first electrode; and a second light emitting diode including an another first electrode, wherein the first electrode partially overlaps the data line and the another first electrode partially overlaps the another data line.
US11335740B2
A display assembly, an electronic device, and a method for assembling a display assembly are provided. The display assembly includes a flexible screen, a cover plate, and a capacitive fingerprint sensor film. The capacitive fingerprint sensor film is disposed between the cover plate and the flexible screen and covers a display surface of the flexible screen, to sense a fingerprint of a finger in contact with the cover plate.
US11335738B2
A display device includes: a lower substrate including a first area, and a second area surrounding the first area; a display layer including a plurality of display elements at the second area, and having a first hole corresponding to the first area; and an upper substrate covering the display layer. The upper substrate includes a lower surface facing the lower substrate, and the lower surface of the upper substrate has a first groove corresponding to the first area.
US11335730B2
A vertical resistive switching memory device is provided that includes a resistive random access memory (ReRAM) stack embedded in a material stack of alternating layers of an interlayer dielectric material and a recessed electrode material. A selector device encapsulates a portion of the ReRAM stack and is present in an undercut region that is laterally adjacent to each of the recessed electrode material layers of the material stack.
US11335726B2
Various embodiments of the present disclosure are directed towards an image sensor having a substrate including a plurality of sidewalls that define a plurality of protrusions along a first side of the substrate. The substrate has a first index of refraction. A photodetector is disposed within the substrate and underlying the plurality of protrusions. A plurality of micro-lenses overlying the first side of the substrate. The micro-lenses have a second index of refraction that is less than the first index of refraction. The micro-lenses are respectively disposed laterally between and directly contact an adjacent pair of protrusions in the plurality of protrusions. Further, the micro-lenses respectively comprise a convex upper surface.
US11335725B2
A method for fabricating an optical sensor includes: forming, over a substrate, a first material layer comprising a first alloy of germanium and silicon having a first germanium composition; forming, over the first material layer, a graded material layer comprising germanium and silicon; and forming, over the graded material layer, a second material layer comprising a second alloy of germanium and silicon having a second germanium composition. The first germanium composition is lower than the second germanium composition and a germanium composition of the graded material layer is between the first germanium composition and the second germanium composition and varies along a direction perpendicular to the substrate.
US11335719B2
Disclosed are a semiconductor package and a method of fabricating the same. The semiconductor package may include a semiconductor chip structure, a transparent substrate disposed on the semiconductor chip structure, a dam placed on an edge of the semiconductor chip structure and between the semiconductor chip structure and the transparent substrate, and an adhesive layer interposed between the dam and the semiconductor chip structure. The semiconductor chip structure may include an image sensor chip and a logic chip, which are in contact with each other, and the image sensor chip may be closer to the transparent substrate than the logic chip.
US11335717B2
A semiconductor device is provided. The semiconductor device includes a substrate and a light-collimating layer. The substrate has a plurality of pixels. The light-collimating layer is disposed on the substrate, and the light-collimating layer includes a transparent material layer, a first light-shielding layer, a second light-shielding layer and a plurality of transparent pillars. The transparent material layer covers the pixels. The first light-shielding layer is disposed on the substrate and the first light-shielding layer has a plurality of holes corresponding to the pixels. The second light-shielding layer is disposed on the first light-shielding layer. The transparent pillars are disposed in the second light-shielding layer.
US11335709B2
Array substrate, display panel, display device, and method for forming array substrate are provided. The array substrate includes a substrate and at least one first thin-film transistor on the substrate. the first thin-film transistor includes a first gate electrode; a first gate electrode insulating layer on a side of the first gate electrode facing away from the substrate; a first active layer on a side of the first gate electrode insulating layer facing away from the first gate electrode; a second gate electrode insulating layer on a side of the first active layer facing away from the first gate electrode insulating layer; a second gate electrode on a side of the second gate electrode insulating layer facing away from the first active layer; and a first source electrode and a first drain electrode on the first active layer facing away from the first gate electrode insulating layer.
US11335702B1
A semiconductor device includes a semiconductor substrate, an insulating film, a ferroelectric film, a first seed layer and a control gate electrode. The semiconductor substrate includes a source region and a drain region which are formed on a main surface of the semiconductor substrate. The insulating film is formed on the main surface of the semiconductor substrate such that the insulating film is positioned between the source region and the drain region in a plan view. The ferroelectric film is formed on the insulating film and includes hafnium and oxygen. The first seed layer is formed on the ferroelectric film. The control gate electrode is formed on the ferroelectric film. A material of the first seed layer includes at least one material of the ferroelectric film and at least one material of the first conductive film.
US11335698B2
A plurality of semiconductor layers have longitudinally a first direction, have a peripheral area surrounded by the plurality of control gate electrodes, and are arranged in a plurality of rows within the laminated body. A controller controls a voltage applied to the control gate electrodes and bit lines. The controller, during a writing operation, applies a first voltage to a first bit line connected to the semiconductor layer positioned in a first row closer to the insulation separating layer, and applies a second voltage larger than the first voltage to a second bit line connected to the semiconductor layer positioned in a second row positioned further from the insulation separating layer with respect to the first row, among the plurality of rows.
US11335693B2
A NOR string includes a number of individually addressable thin-film storage transistors sharing a bit line, with the individually addressable thin-film transistors further grouped into a predetermined number of segments. In each segment, the thin-film storage transistors of the segment share a source line segment, which is electrically isolated from other source line segments in the other segments within the NOR string. The NOR string may be formed along an active strip of semiconductor layers provided above and parallel a surface of a semiconductor substrate, with each active strip including first and second semiconductor sublayers of a first conductivity and a third semiconductor sublayer of a second conductivity, wherein the shared bit line and each source line segment are formed in the first and second semiconductor sublayers, respectively.
US11335692B2
The present disclosure provides a non-volatile flash memory device and a manufacturing method thereof. The non-volatile flash memory device comprises at least a plurality of memory cells in a memory area. The manufacturing method comprises: providing a substrate, and defining the memory area of the non-volatile flash memory device on the substrate; forming a plurality of stack gates of the plurality of memory cells on a substrate corresponding to the memory area, and the top of each stack gate is a memory control gate of the memory cell; etching the memory control gates to reduce the height of the memory control gates with the fluid photoresist filled among the plurality of stack gates of the plurality of memory cells as a mask; and removing the fluid photoresist.
US11335685B2
Disclosed are semiconductor memory devices and methods of fabricating the same. The semiconductor memory device comprises a first semiconductor pattern that is on a substrate and that includes a first end and a second end that face each other, a first conductive line that is adjacent to a lateral surface of the first semiconductor pattern between the first and second ends and that is perpendicular to a top surface of the substrate, a second conductive line that is in contact with the first end of the first semiconductor pattern, is spaced part from the first conductive line, and is parallel to the top surface of the substrate, and a data storage pattern in contact with the second end of the first semiconductor pattern. The first conductive line has a protrusion that protrudes adjacent to the lateral surface of the first semiconductor pattern.
US11335670B2
A manufacturing method of a light emitting diode (LED) package structure includes the following steps. A carrier is provided. A redistribution layer is formed on the carrier. A plurality of active devices are formed on the carrier. A plurality of LEDs are transferred on the redistribution layer. The LEDs and the active devices are respectively electrically connected to the redistribution layer. The active devices are adapted to drive the LEDs, respectively. A molding compound is formed on the redistribution layer to encapsulate the LEDs. The carrier is removed to expose a bottom surface of the redistribution layer.
US11335668B2
The present disclosure relates to a semiconductor package and a manufacturing method thereof. The method includes stacking semiconductor chips using a thermo-compression bonding (TCB) method, where defects are minimized for increased reliability. The semiconductor package includes an interface chip including a first test pad, a bump pad provided inside the first test pad, and a first through silicon via (TSV) provided between the first test pad and the bump pad; at least one memory chip, which is stacked on the interface chip and includes a second test pad, a dummy pad provided inside the second test pad, and a second TSV provided between the second test pad and the dummy pad; and an adhesive layer provided between the interface chip and the at least one memory chip. wherein no bump is provided on the first test pad and the second test pad.
US11335665B2
Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.
US11335656B2
A semiconductor device including a first die and a second die bonded to one another. The first die includes a first passivation layer over a substrate, and first bond pads in the first passivation layer. The second die includes a second passivation layer, which may be bonded to the first passivation layer, and second bond pads in the second passivation layer, which may be bonded to the first bond pads. The second bond pads include inner bond pads and outer bond pads. The outer bond pads may have a greater diameter than the inner bond pads as well as the first bond pads.
US11335655B2
A package structure include a ground plate, a semiconductor die, a molding compound, and an antenna element. The semiconductor die is located over the ground plate. The molding compound is located over the semiconductor die. The antenna element is located in the molding compound and overlaps with the ground plate along a stacking direction of the ground plate, the semiconductor die and the molding compound. The antenna element has a first side levelled with a first surface of the molding compound, and the ground plate is located between the semiconductor die and the antenna element.
US11335652B2
A semiconductor device package that incorporates a waveguide usable for high frequency applications, such as radar and millimeter wave is provided. Embodiments employ a rigid-flex printed circuit board structure that can be folded to form the waveguide while, at the same time, mounting one or more semiconductor device die or packages. Embodiments reduce both the area of the mounted package and the distance signals need to travel between the semiconductor device die and antennas associated with the waveguide.
US11335649B2
Various embodiments of laminated planar bus structures that minimize electromagnetic interference (EMI) and parasitic inductance are described. In one embodiment, a laminated planar bus structure may include a plurality of stacked conductive layers and a plurality of stacked insulation layers. The plurality of stacked conductive layers may include positive and negative conductive layers, and conductive ground layers stacked as outer layers as to enclose vertically the positive and the negative conductive layers. In another embodiment, the laminated planar bus structure may include a middle ground layer stacked in between the positive and the negative conductive layers to provide additional reduction in electric field strength. A laminated planar bus structure that is integrated with other power electronics components is also presented.
US11335648B2
A method for fabricating a semiconductor structure is provided. The method includes forming a semiconductor chip; providing a printed circuit board; and forming an adhesive layer between a connection surface of the semiconductor chip and the printed circuit board to bond the semiconductor chip with the printed circuit board. The semiconductor chip includes a plurality of cutting tracks intersected with each other to enclose an area having corner regions. The connection surface of the semiconductor chip includes a plurality of conductive bumps and a plurality of first openings are formed in each of the corner regions.
US11335642B2
Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a first die comprising a first face and a second face; and a second die, the second die comprising a first face and a second face, wherein the second die further comprises a plurality of first conductive contacts at the first face and a plurality of second conductive contacts at the second face, and the second die is between first-level interconnect contacts of the microelectronic assembly and the first die.
US11335638B2
The present disclosure describes a method for reducing RC delay in radio frequency operated devices or devices that would benefit from an RC delay reduction. The method includes forming, on a substrate, a transistor structure having source/drain regions and a gate structure; depositing a first dielectric layer on the substrate to embed the transistor structure; forming, within the first dielectric layer, source/drain contacts on the source/drain regions of the transistor structure; depositing a second dielectric layer on the first dielectric layer; forming metal lines in the second dielectric layer; forming an opening in the second dielectric layer between the metal lines to expose the first dielectric layer; etching, through the opening, the second dielectric layer between the metal lines and the first dielectric layer between the source/drain contacts; and depositing a third dielectric layer to form an air-gap in the first and second dielectric layers and over the transistor structure.
US11335637B2
A semiconductor device includes a substrate having an active region, a gate structure disposed on the active region, a source/drain region disposed in the active region at a side of the gate structure, a first interlayer insulating layer and a second interlayer insulating layer sequentially disposed on the gate structure and the source/drain region with an etch stop layer interposed therebetween, a first contact plug connected to the source/drain region through the first interlayer insulating layer, a second contact plug connected to the gate structure through the first interlayer insulating layer and the second interlayer insulating layer, a first metal line disposed on the second interlayer insulating layer, and having a metal via disposed in the second interlayer insulating layer and connected to the first contact plug, and a second metal line disposed on the second interlayer insulating layer, and directly connected to the second contact plug.
US11335634B2
A method for forming a chip package structure is provided. The method includes providing a wiring substrate. The method includes sequentially forming a nickel-containing layer and a gold-containing layer over the first pad. The method includes forming a conductive protection layer covering the gold-containing layer over the nickel-containing layer. The method includes bonding a chip to the wiring substrate through a conductive bump and a flux layer surrounding the conductive bump. The conductive bump is between the second pad and the chip. The method includes removing the flux layer while the conductive protection layer covers the nickel-containing layer.
US11335628B2
A semiconductor package includes a lead frame, a semiconductor chip, a plurality of three-dimensional wrings, and a mold resin. The semiconductor chip is mounted on the lead frame. The mold resin covers a part of the lead frame, the semiconductor chip, and a part of each of the plurality of three-dimensional wirings.
US11335624B2
A liquid discharge apparatus includes a print head discharging a liquid and a control circuit controlling an operation of the print head. the print head includes a connector having a first terminal, a second terminal, a third terminal, and a fourth terminal, a first integrated circuit, a circuit substrate on which the connector and the first integrated circuit are provided and which has first wiring, second wiring, third wiring, fourth wiring, fifth wiring, and sixth wiring, and a first wiring substrate, in which the first wiring electrically couples the first terminal and the first integrated circuit to each other, the fifth wiring electrically couples the first terminal and the first integrated circuit to each other, and the sixth wiring electrically couples the first integrated circuit and the first wiring substrate to each other.
US11335622B2
A die of an integrated circuit and an upper layer of a circuit assembly are thermally connected by applying a thermal interface material (TIM) on the die, such that the TIM is between the die and an upper layer. The TIM comprises an emulsion of liquid metal droplets and uncured polymer. The method further comprises compressing the circuit assembly thereby deforming the liquid metal droplets and curing the thermal interface material thereby forming the circuit assembly.
US11335620B2
Embodiments include a microelectronic device package structure having an inductor at least partially embedded within a substrate. At least one thermal solution structure may be on a surface of the inductor, and may be thermally coupled with the inductor. The one or more thermal solution structures provide a thermal pathway for cooling for the inductor, and extend a thermal time constant of the inductor.
US11335618B2
An apparatus is provided which comprises: one or more pads comprising metal on a first substrate surface, the one or more pads to couple with contacts of an integrated circuit die, one or more substrate layers comprising dielectric material, one or more conductive contacts on a second substrate surface, opposite the first substrate surface, the one or more conductive contacts to couple with contacts of a printed circuit board, one or more inductors on the one or more substrate layers, the one or more inductors coupled with the one or more conductive contacts and the one or more pads, and highly thermally conductive material between the second substrate surface and a printed circuit board surface, the highly thermally conductive material contacting the one or more inductors. Other embodiments are also disclosed and claimed.
US11335612B2
A test site and method are herein disclosed for predicting E-test structure (in-die structure) and/or device performance. The test site comprises an E-test structure and OCD-compatible multiple structures in the vicinity of the E-test structure to allow optical scatterometry (OCD) measurements. The OCD-compatible multiple structures are modified by at least one modification technique selected from (a) multiplication type modification technique, (b) dummification type modification technique, (c) special Target design type modification technique, and (d) at least one combination of (a), (b) and (c) for having a performance equivalent to the performance of the E-test structure.
US11335609B2
A micro detector includes a substrate, a fin structure, a floating gate, a sensing gate, a reading gate and an antenna layer. The fin structure is located on the substrate. The floating gate is located on the substrate, and the floating gate is vertically and crossly arranged with the fin structure. The sensing gate is located at one side of the fin structure. The reading gate is located at the other side of the fin structure. The antenna layer is located on the sensing gate and is connected with the sensing gate. An induced charge is generated when the antenna layer is contacted with an external energy source, and the induced charge is stored in the floating gate.
US11335602B2
A method of forming a microelectronic device comprises forming a microelectronic device structure comprising a base structure; a doped semiconductive material overlying the base structure; a stack structure overlying the doped semiconductive material; semiconductive structures extending from within the base structure, through the doped semiconductive structure, and into a lower portion of the stack structure; cell pillar structures horizontally aligned with the semiconductive structures and vertically extending through an upper portion of the stack structure; and digit line structures vertically overlying the stack structure. An additional microelectronic device structure comprising control logic devices is formed. The microelectronic device structure is attached to the additional microelectronic device structure to form an assembly. The base structure and portions of the semiconductive structures are removed. The doped semiconductive material is then patterned to form at least one source structure coupled to the cell pillar structures. Devices and systems are also described.
US11335598B2
Embodiments include an interconnect structure and methods of forming such an interconnect structure. In an embodiment, the interconnect structure comprises a first interlayer dielectric (ILD) and a first interconnect layer with a plurality of first conductive traces partially embedded in the first ILD. In an embodiment, an etch stop layer is formed over surfaces of the first ILD and sidewall surfaces of the first conductive traces. In an embodiment, the interconnect structure further comprises a second interconnect layer that includes a plurality of second conductive traces. In an embodiment, a via between the first interconnect layer and the second interconnect layer may be self-aligned with the first interconnect layer.
US11335596B2
Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece that includes a substrate and an interconnect structure. The interconnect structure includes a first conductive feature disposed within a first inter-level dielectric layer. A blocking layer is selectively formed on the first conductive feature without forming the blocking layer on the first inter-level dielectric layer. An alignment feature is selectively formed on the first inter-level dielectric layer without forming the alignment feature on the blocking layer. The blocking layer is removed from the first conductive feature, and a second inter-level dielectric layer is formed on the alignment feature and on the first conductive feature. The second inter-level dielectric layer is patterned to define a recess for a second conductive feature, and the second conductive feature is formed within the recess.
US11335590B2
Disclosed is a semiconductor processing approach wherein a wafer twist is employed to increase etch rate, at select locations, along a hole or space end arc. By doing so, a finished hole may more closely resemble the shape of the incoming hole end. In some embodiments, a method may include providing an elongated contact hole formed in a semiconductor device, and etching the elongated contact hole while rotating the semiconductor device, wherein the etching is performed by an ion beam delivered at a non-zero angle relative to a plane defined by the semiconductor device. The elongated contact hole may be defined by a set of sidewalls opposite one another, and a first end and a second end connected to the set of sidewalls, wherein etching the elongated contact hole causes the elongated contact hole to change from an oval shape to a rectangular shape.
US11335585B2
Disclosed is a substrate displacing assembly so as to improve its durability during a semiconductor processing. In one embodiment, a semiconductor manufacturing system, includes, a substrate holder, wherein the substrate holder is configured with a plurality of pins; and a substrate displacing assembly for displacing a substrate on the substrate holder in a first direction perpendicular to the top surface of the substrate holder through the plurality of pins, wherein the substrate displacing assembly comprises a pair of load forks, a coupler and a driving shaft, wherein the pair of load forks comprises a fork region and a base region, wherein the coupler is mechanically coupled to the base region through at least one first joining screw extending in the first direction, wherein the coupler is further mechanically coupled to the driving shaft through a second joining screw extending in the first direction.
US11335584B2
A method for disassembling a stack of at least three substrates. The invention relates to the techniques for transferring thin films in the microelectronics field. It proposes a method for disassembling a stack of at least three substrates having between them two interfaces, one interface of which has an adhesion energy and an interface of which has an adhesion energy, with less than, the method comprising: 1) implementing a removal of material on the first substrate, in order to expose a surface of the second substrate, 2) transferring the stack onto a flexible adhesive film so that the surface has, with an adhesive layer of the film, an adhesion energy greater than, and 3) disassembling the third substrate at the interface between the second substrate and the third substrate. The method makes it possible to open the stack via the interface thereof with the highest adhesion energy.
US11335571B2
A semiconductor device includes a package substrate, a semiconductor chip and a solder bump. The semiconductor chip is disposed on the package substrate. The package substrate includes a first electrode pad, and a first insulating film formed such that the first insulating film exposes a first portion of a surface of the first electrode pad. The semiconductor chip includes a second electrode pad and a second insulating film formed such that the second insulating film exposes a second portion of a surface of the second electrode pad. The second electrode pad is formed on the first electrode pad through the solder bump. L2/L1 is 0.63 or more in a cross section passing through the first electrode pad, the solder bump and the second electrode pad. A first length of the first portion and a second length of the second portion are defined as L1 and L2, respectively.
US11335569B2
A method of manufacturing a conductive wire structure including following steps is provided. A conductive layer is formed on a substrate. A rectangular ring spacer is formed on the conductive layer by a self-aligned double patterning process. A patterned photoresist layer is formed. The patterned photoresist layer exposes a first portion and a second portion of the rectangular ring spacer. The first and second portions are located at two corners on a diagonal of the rectangular ring spacer. The first and second portions are removed by using the patterned photoresist layer as a mask to form a first spacer and a second spacer. The first spacer and the second spacer are L-shaped. The patterned photoresist layer is removed. A pattern of the first spacer and a pattern of the second spacer are transferred to the conductive layer to form an L-shaped first conductive wire and an L-shaped second conductive wire.
US11335568B2
A method for forming a semiconductor structure is provided. The method includes: forming first and second hard mask layers and a target layer on a substrate; patterning the second hard mask layer to form patterned second hard masks including a second wide mask and second narrow masks; and forming spacers on sidewalls of the second wide mask and the second narrow masks. Then, a photoresist layer is formed to cover the second wide mask and the spacers on the sidewalls of the second wide mask. The second narrow masks and the photoresist layer are removed. And, the first hard mask layer is etched with the spacers and the second wide mask together as a mask to form patterned first hard masks on the target layer, wherein the spacers define a first line width, and the second wide mask and the pair of spacers define a second line width.
US11335563B2
A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.
US11335549B2
An excimer lamp, which includes a first lamp cap, a second lamp cap, a first electrode head, a second electrode head, a conductive heat dissipation rod, a light-transparent annular sleeve, and a conductive annular net. The heat dissipation rod and conductive annular net are respectively connected to the first and second electrode heads to excite an excimer gas in the light-transparent annular sleeve. Inside the excimer lamp the, a large amount of heat can be conducted and dissipated through the conductive heat dissipation rod, and then through the heat dissipation of the first lamp cap or by heat conductive annular rings between sections of the lamp. At the same time, the conductive annular nets can also conduct and dispatch a large amount of above mentioned heat; the heat may be further conducted and dispatched through the second lamp cap or through the heat conductive annular rings, if present.
US11335540B2
In one embodiment, an impedance matching network includes a mechanically variable capacitor (MVC), a second variable capacitor, and a control circuit. The control circuit carries out a first process of determining a second variable capacitor configuration for reducing a reflected power at the RF source output, and altering the second variable capacitor to the second variable capacitor configuration. The control circuit also carries out a second process of determining an RF source frequency, and, upon determining that the RF source frequency is outside, at a minimum, or at a maximum of a predetermined frequency range, determining a new MVC configuration to cause the RF source frequency, according to an RF source frequency tuning process, to be altered to be within or closer to the predetermined frequency range. The determination of the new MVC configuration is based on the RF source frequency and the predetermined frequency range.
US11335539B2
A method for optimizing delivery of power to a plasma chamber is described. The method includes dividing each cycle of a low frequency (LF) radio frequency generator (RFG) into multiple time intervals. During each of the time intervals, a frequency offset of a high frequency (HF) RFG is generated for which the delivery of power is maximized. The frequency offsets provide a substantially inverse relationship compared to a voltage signal of the LF RFG for each cycle of the voltage signal. The frequency offsets for the time intervals are multiples of the low frequency. The substantially inverse relationship facilitates an increase in the delivery of power to the electrode. A total range of the frequency offsets from a reference HF frequency over the LF RF cycle depends on a power ratio of power that is supplied by the LF RFG and power that is supplied by the HF RFG.
US11335538B2
The invention relates to a filter unit for filtering multiple pulse signals comprising a number of filter circuits, which are connected in parallel. Each filter circuit comprises an input and an output, wherein the input is configured to receive an amplitude of an input signal and the output is configured to activate an output signal. Each filter circuit has an allocated filter level and further comprises a pulse level detection circuit configured to detect a change of state of a pulse level of the input signal. The change of state comprises a transition from a first pulse level to a second pulse level and if the pulse level corresponds to the allocated filter level of the filter circuit the output of said filter circuit is activated.
US11335535B2
Provided is a charged particle beam apparatus capable of estimating an internal device structure of a sample. The charged particle beam apparatus includes an electron beam optical system, a detector, and a calculator. The electron beam optical system irradiates a plurality of irradiation points on a sample, which are different in position or time, with an electron beam. The detector detects electrons emitted from the sample in response to irradiation of the electron beam by the electron beam optical system. The calculator calculates a dependence relationship between the irradiation points based on the electrons detected by the detector at the plurality of irradiation points.
US11335529B2
A compound field emitter (CFE) includes a first surface possessing a field enhancement factor >1, and a second surface possessing one or both of a field enhancement factor >1, or a low work function, wherein the second surface is coated, formed or applied upon the first surface. The second surface has a characteristic size at least 3 times smaller than the first surface, and the outer surface includes a coating of calcium aluminate 12CaO-7Al2O3.
US11335526B2
A coil carrier for an electromagnetic switch of a starting device including a cavity enclosed by a carrier wall for winding of a coil wire. The carrier wall may extend in an axial direction from a first end wall to a second end wall. The coil carrier may include at least one separating body protruding radially, and extending in a circumferential direction, on a side of the carrier wall facing away from the cavity. The at least one separating body may have a recess which separates a first separating body end of the at least one separating body from a second separating body end of the at least one separating body in the circumferential direction. The at least one separating body may have an axially extending body width that decreases along the circumferential direction.
US11335523B2
A support for a high-voltage electric switch includes a housing, a shaft, and an intermediate member positioned between the housing and the shaft. The shaft extends at least partially through the housing, and the shaft is supported for rotation about an axis. The intermediate member is supported for rotation relative to the shaft and supported for rotation relative to the housing.
US11335504B2
A film capacitor includes a main body portion. A dielectric film of the main body portion includes an insulation margin in a first direction. A first metal film and a second metal film are each separated by first slits which each includes a first end which is at an angle of θ1 to the second side face, and second slits. The second slit is connected at a contact point to the first slit, and includes a second end which is located on a negative side in the first direction relative to the contact point. The second end is positioned in alignment with a first end of a first slit which is continuous with the second slit adjacent thereto on the negative side in the first direction. A value of tan (θ1) is in a range of 0.15 or more and 0.35 or less.
US11335500B2
The invention provides a method and a device for producing a winding element from a supplied wire, in particular from a round copper wire, said method and device allowing the economical and flexible production of a winding element which, when subsequently used in the field of electrical engineering as a coil or inductor fitted in a stator, ensures the highest possible groove filling factor. For this purpose, the wire is wound to a three-dimensional shape and the cross section of the wire is changed simultaneously, as a result of which separate method steps and therefore tool arrangements for three-dimensional winding of the wire as well as the change of the cross-section of the wire can advantageously be dispensed with.
US11335496B2
A coil component includes a body having a bottom surface and a top surface opposing each other in one direction, and a plurality of walls each connecting the bottom surface to the top surface of the body; recesses respectively formed in both front and rear surfaces of the body opposing each other among the plurality of walls of the body and extending up to the bottom surface of the body; a coil portion buried in the body and including first and second lead-out portions exposed to internal walls and lower ledge surfaces of the recesses; first and second external electrodes respectively including connection portions disposed in the recesses and extended portions disposed on the bottom surface of the body, and connected to the coil portion; a shielding layer including a cap portion disposed on the top surface of the body and side wall portions respectively disposed on the plurality of walls of the body; and an insulating layer disposed between the body and the shielding layer and extending onto lower ledge surfaces and internal walls of the recesses to cover the connection portions.
US11335488B1
A magnetic energy system including a pathway having inclined portions of the pathway contiguous with declined portions of the pathway and an object adapted to move on the pathway by descending a declined portion of the pathway under the influence of gravity and ascending the contiguous inclined portion of the pathway under the combined influence of kinetic energy and a magnetic flux field interaction with release of the object from the magnetic flux field interaction at a pathway height equal to or greater than the initial height of the object on the preceding declined portion of the pathway.
US11335485B2
Provided is a multilayer electrical steel sheet having low high-frequency iron loss and high magnetic flux density. The multilayer electrical steel sheet has an inner layer and surface layers provided on both sides of the inner layer, in which the surface layers and inner layer have predetermined chemical compositions, the multilayer electrical steel sheet having: ΔSi of 0.5 mass % or more, ΔSi being defined as a difference between a Si content in the surface layer [Si]1 and a Si content in the inner layer [Si]0 represented by [Si]1−[Si]0; Δλ1.0/400 of 1.0×10−6 or less, Δλ1.0/400 being defined as an absolute value of the difference between a magnetostriction of the surface layer λ1.0/400,1 and a magnetostriction of the inner layer λ1.0/400,0; a sheet thickness t of 0.03 mm to 0.3 mm, and a ratio of a total thickness of the surface layers t1 to t of from 0.10 to 0.70.
US11335481B2
An oxide superconductor of an embodiment includes an oxide superconductor layer having a continuous Perovskite structure containing rare earth elements, barium (Ba), and copper (Cu). The rare earth elements contain a first element which is praseodymium (Pr), at least one second element selected from the group consisting of neodymium (Nd), samarium (Sm), europium (Eu), and gadolinium (Gd), at least one third element selected from the group consisting of yttrium (Y), terbium (Tb), dysprosium (Dy), and holmium (Ho), and at least one fourth element selected from the group consisting of erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu).