- 专利标题: Low impedance multi-conductor layered bus structure with shielding
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申请号: US16879078申请日: 2020-05-20
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公开(公告)号: US11335649B2公开(公告)日: 2022-05-17
- 发明人: Jun Wang , Rolando Burgos , Dushan Boroyevich , Joshua Stewart , Yue Xu
- 申请人: VIRGINIA TECH INTELLECTUAL PROPERTIES, INC.
- 申请人地址: US VA Blacksburg
- 专利权人: VIRGINIA TECH INTELLECTUAL PROPERTIES, INC.
- 当前专利权人: VIRGINIA TECH INTELLECTUAL PROPERTIES, INC.
- 当前专利权人地址: US VA Blacksburg
- 代理机构: Thomas | Horstemeyer, LLP.
- 主分类号: H01L23/60
- IPC分类号: H01L23/60 ; H01L23/50 ; H01L23/522
摘要:
Various embodiments of laminated planar bus structures that minimize electromagnetic interference (EMI) and parasitic inductance are described. In one embodiment, a laminated planar bus structure may include a plurality of stacked conductive layers and a plurality of stacked insulation layers. The plurality of stacked conductive layers may include positive and negative conductive layers, and conductive ground layers stacked as outer layers as to enclose vertically the positive and the negative conductive layers. In another embodiment, the laminated planar bus structure may include a middle ground layer stacked in between the positive and the negative conductive layers to provide additional reduction in electric field strength. A laminated planar bus structure that is integrated with other power electronics components is also presented.
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