公开(公告)号：US20240081077A1

公开(公告)日：2024-03-07

申请号：US17901777

申请日：2022-09-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd. ,  National Yang Ming Chiao Tung University

发明人： Po-Tsun Liu ,  Meng-Han Lin ,  Zhen-Hao Li ,  Tsung-Che Chiang ,  Bo-Feng Young ,  Hsin-Yi Huang ,  Sai-Hooi Yeong ,  Yu-Ming Lin

IPC分类号： H01L27/11597 ,  H01L21/28 ,  H01L27/11587 ,  H01L27/1159 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC分类号： H01L27/11597 ,  H01L27/11587 ,  H01L27/1159 ,  H01L29/0673 ,  H01L29/40111 ,  H01L29/41733 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/6684 ,  H01L29/775 ,  H01L29/78696

摘要： A transistor includes a first semiconductor layer, a second semiconductor layer, a semiconductor nanosheet, a gate electrode and source and drain electrodes. The semiconductor nanosheet is physically connected to the first semiconductor layer and the second semiconductor layer. The gate electrode wraps around the semiconductor nanosheet. The source and drain electrodes are disposed at opposite sides of the gate electrode. The first semiconductor layer surrounds the source electrode, the second semiconductor layer surrounds the drain electrode, and the semiconductor nanosheet is disposed between the source and drain electrodes.

公开(公告)号：US20230397426A1

公开(公告)日：2023-12-07

申请号：US17832673

申请日：2022-06-05

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Wei Jiang ,  TsuChing Yang ,  Sheng-Chih Lai ,  Feng-Cheng Yang ,  Chung-Te Lin

IPC分类号： H01L27/11597 ,  H01L27/1159

CPC分类号： H01L27/11597 ,  H01L27/1159

摘要： A 3D memory array including multiple memory cells and a method of manufacturing the same are provided. Each memory cell includes a first isolation structure, source and drain electrodes, a gate layer, a channel layer and a memory layer. The source and drain electrodes are disposed on opposite sides of the first isolation structure, and the source and drain electrodes comprise kink portions. The gate layer is disposed beside the source and drain electrodes and the first isolation structure. The channel layer is disposed between the gate layer and the source electrode, the first isolation structure and the drain electrode, and the channel layer extends between the source and drain electrodes and covers the kink portions of the source and drain electrodes. The memory layer is disposed between the gate layer and the channel layer and extends beside the gate layer and extends beyond the channel layer.

公开(公告)号：US20230328998A1

公开(公告)日：2023-10-12

申请号：US17718071

申请日：2022-04-11

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Meng-Han LIN ,  Chia-En HUANG

IPC分类号： H01L27/1159 ,  H01L27/11597 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L29/51

CPC分类号： H01L27/1159 ,  H01L27/11597 ,  H01L29/78391 ,  H01L29/6684 ,  H01L29/40111 ,  H01L29/516 ,  H01L29/7855 ,  H01L29/66795

摘要： A memory device comprises a word line, a gate dielectric layer, a semiconductor layer, a source line, and a resistance-switchable element. The word line is over a substrate. The gate dielectric layer is on a sidewall of the word line. The semiconductor layer is on a sidewall of the gate dielectric layer. The source line is in contact with a first region of a sidewall of the semiconductor layer. The resistance-switchable element is in contact with a second region of the sidewall of the semiconductor layer.

公开(公告)号：US20230269946A1

公开(公告)日：2023-08-24

申请号：US17675391

申请日：2022-02-18

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Meng-Han LIN ,  Feng-Cheng YANG

IPC分类号： H01L27/11597 ,  H01L27/11587 ,  G11C16/04 ,  H01L23/528

CPC分类号： H01L27/11597 ,  H01L27/11587 ,  G11C16/0483 ,  H01L23/5283

摘要： A 3D memory array includes a tableland feature formed with multiple 3D memory sub-arrays that are arranged in an X-axis direction. Each 3D memory sub-array includes multiple memory cells that are distributed in multiple columns arranged in the X-axis direction, multiple bit lines extending in a Z-axis direction, multiple source lines extending in the Z-axis direction, and multiple word lines extending in a Y-axis direction. Each memory cell includes a first electrode, a second electrode and a gate electrode. Each bit line interconnects the first electrodes of some of the memory cells aligned in the Z-axis direction. Each bit line is electrically connected to another bit line of the same 3D memory sub-array, which is aligned with the bit line in the X-axis direction, and is electrically isolated from the bit lines of another 3D memory sub-array.

公开(公告)号：US20230262986A1

公开(公告)日：2023-08-17

申请号：US17669802

申请日：2022-02-11

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Wen-Ling LU ,  Chia-En HUANG ,  Ya-Yun CHENG ,  Yi-Ching LIU ,  Huan-Sheng WEI ,  Chung-Wei WU

IPC分类号： H01L27/11597 ,  H01L27/11587 ,  G11C5/06

CPC分类号： H01L27/11597 ,  G11C5/063 ,  H01L27/11587

摘要： A ferroelectric memory device includes a semiconductor structure, a stack structure disposed on the semiconductor structure and including multiple dielectric layers and multiple conductive layers that are alternatingly stacked, and multiple memory arrays extending through the stack structure. Each of the memory arrays includes two spaced-apart memory segments connecting to the stack structure, multiple spaced-apart channel portions each being connected to a corresponding one of the memory segments, and multiple pairs of source/bit lines that are spaced apart from each other. Each of the pairs of the source/bit lines is connected between corresponding two of the channel portions. The ferroelectric memory device further includes multiple carrier structures each being connected to one of the source/bit lines in a corresponding one of the pairs of the source/bit lines, and being separated from the other one of the source/bit lines in the corresponding one of the pairs of the source/bit lines.

公开(公告)号：US20230238324A1

公开(公告)日：2023-07-27

申请号：US17586740

申请日：2022-01-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chung-Liang Cheng

IPC分类号： H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L27/24 ,  H01L27/11597 ,  H01L27/108 ,  H01L27/22

CPC分类号： H01L23/5286 ,  H01L27/228 ,  H01L27/2454 ,  H01L27/10805 ,  H01L27/11597 ,  H01L29/0669 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/78696

摘要： A semiconductor device includes a first transistor formed on a first side of a substrate. The semiconductor device includes a first power rail structure vertically disposed over the first transistor, a second power rail structure vertically disposed over the first power rail structure, and a memory portion vertically disposed over the second power rail structure. The first power rail structure, and a second power rail structure, and the memory portion are all disposed on a second side of the substrate opposite to the first side.

公开(公告)号：US20230225131A1

公开(公告)日：2023-07-13

申请号：US17574518

申请日：2022-01-12

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Meng-Han Lin ,  Han-Jong Chia ,  Feng-Cheng Yang

IPC分类号： H01L27/11597 ,  H01L27/11587

CPC分类号： H01L27/11597 ,  H01L27/11587

摘要： A memory device includes a first etch stop layer, an etch stop pattern, a second etch stop layer, a plurality of stacks and a first conductive pillar. The etch stop pattern is disposed in the first etch stop layer. The second etch stop layer is disposed on the first etch stop layer and the etch stop pattern, wherein a material of the etch stop pattern is different from a material of the first etch stop layer and a material of the second etch stop layer. The stacks are disposed on the second etch stop layer. The first conductive pillar is disposed between the stacks, wherein the first conductive pillar extends along the stacks and the second etch stop layer to be in physical contact with the etch stop pattern.

公开(公告)号：US20230225130A1

公开(公告)日：2023-07-13

申请号：US17572623

申请日：2022-01-10

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Peng-Chun Liou ,  Zhiqiang Wu ,  Chung-Wei Wu ,  Ya-Yun Cheng

IPC分类号： H01L27/11597 ,  H01L27/11587

CPC分类号： H01L27/11597 ,  H01L27/11587

摘要： A ferroelectric memory device includes a multi-layer stack, a ferroelectric layer, and channel layers. The multi-layer stack is disposed on a substrate and includes conductive layers and dielectric layers stacked alternately. The ferroelectric layer has a curvy profile and is disposed along sidewalls of the conducive layers and sidewalls of the dielectric layers. The channel layers are separated from each other and disposed on the ferroelectric layer, and correspond to the conductive layers respectively.

公开(公告)号：US20230206976A1

公开(公告)日：2023-06-29

申请号：US17875730

申请日：2022-07-28

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Kyunghwan LEE ,  Yongseok KIM ,  Hyuncheol KIM ,  Jongman PARK ,  Dongsoo WOO ,  Minjun LEE

IPC分类号： G11C11/22 ,  H01L27/11597 ,  H01L21/28

CPC分类号： G11C11/223 ,  G11C11/2255 ,  G11C11/2257 ,  H01L27/11597 ,  H01L29/40111

摘要： A semiconductor device including a substrate; a stack including electrodes and a channel separation pattern, the electrodes being stacked on the substrate and spaced apart from each other, and the channel separation pattern being between adjacent electrodes; and a vertical structure penetrating the stack, wherein the vertical structure includes a conductive pillar, a channel structure, and an interposing layer between the conductive pillar and the channel structure, the channel structure includes first and second channel layers vertically spaced apart from each other by the channel separation pattern, the electrodes include first and second electrodes, which are connected to the first and second channel layers, the channel separation pattern is between the first channel layer and the second channel layer, and the channel separation pattern is between one second electrode that is connected to the first channel layer and one first electrode that is connected to the second channel layer.

公开(公告)号：US11683936B2

公开(公告)日：2023-06-20

申请号：US17141915

申请日：2021-01-05

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Meng-Han Lin ,  Chia-En Huang

IPC分类号： H01L27/11597 ,  H01L27/11587 ,  H10B51/20 ,  H10B51/10

CPC分类号： H01L27/11597 ,  H01L27/11587

摘要： A semiconductor memory structure and method of manufacturing a semiconductor memory structure are provided. The semiconductor memory structure includes alternatively arranged stacking portions and cell regions. Each cell region includes two ferroelectric layers formed along the adjacent stacking portions; and at least one central portion disposed between the ferroelectric layers and including a first conductive structure and a second conductive structure separated by a channel isolation structure as well as two semiconductor layers formed along the ferroelectric layers. The first conductive structure includes a contact portion and an extension portion. The contact portion is disposed between the semiconductor layers. The extension portion extends from the contact portion to the channel isolation structure and is separated from the semiconductor layers through dielectric layers.