公开(公告)号：US20230115434A1

公开(公告)日：2023-04-13

申请号：US17868944

申请日：2022-07-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minjun LEE ,  YONGSEOK KIM ,  HYUNCHEOL KIM ,  JONGMAN PARK ,  DONGSOO WOO ,  KYUNGHWAN LEE

IPC: H01L27/11507

Abstract: Disclosed is a semiconductor memory device including a substrate, a plurality of source lines extending in a first direction on the substrate, a plurality of word lines crossing the source lines and extending in a second direction different from the first direction, a plurality of bit lines crossing the source lines and the word lines and extending in a third direction different from the first direction and the second direction, and a plurality of memory cells disposed at intersections between the source lines, the word lines, and the bit lines. The first, second, and third directions are parallel to a top surface of the substrate.

公开(公告)号：US20230180453A1

公开(公告)日：2023-06-08

申请号：US18054986

申请日：2022-11-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyuncheol KIM ,  Yongseok KIM ,  Kyunghwan LEE ,  Minjun LEE ,  Daewon HA

IPC: H01L27/108

CPC classification number: H01L27/10802

Abstract: A memory device is provided. The memory device includes a substrate, a fin structure on the substrate, a gate structure on the fin structure, a first source/drain at one end of the fin structure, and a second source/drain at the other end of the fin structure, wherein the gate structure includes a trap layer, a blocking layer, and a gate electrode layer sequentially stacked on the fin structure, the first source/drain is doped with or has incorporated therein dopants of a first conductivity-type, and the second source/drain is doped with or has incorporated therein dopants of a second conductivity-type dopants that are different from the dopants of the first conductivity-type.

公开(公告)号：US20230101700A1

公开(公告)日：2023-03-30

申请号：US17881747

申请日：2022-08-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghwan LEE ,  Yongseok KIM ,  Hyuncheol KIM ,  Jongman PARK ,  Dongsoo WOO ,  Minjun LEE

IPC: H01L27/108

Abstract: A semiconductor memory device may include first and second bit lines spaced apart from each other, an interlayer insulating layer covering the first and second bit lines and including a groove extending to cross both of the first and second bit lines, a first channel pattern connected to the first bit line and in contact with an inner side surface of the groove and covering a top surface of the interlayer insulating layer, a second channel pattern connected to the second bit line and in contact with an opposite inner side surface of the groove and covering the top surface of the interlayer insulating layer, a word line in the groove, first and second electrodes on the interlayer insulating layer and in contact with the first and second channel patterns, respectively, and a dielectric layer between the first and second electrodes.

公开(公告)号：US20240306398A1

公开(公告)日：2024-09-12

申请号：US18594350

申请日：2024-03-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongseok KIM ,  Yukio HAYAKAWA ,  Minjun LEE ,  Bongyong LEE ,  Siyeon CHO

IPC: H10B53/30 ,  H10B53/20

CPC classification number: H10B53/30 ,  H10B53/20

Abstract: A three-dimensional non-volatile memory device includes a plurality of horizontal word lines spaced apart from each other in a vertical direction, a pillar gate electrode buried in a first channel hole that passes through the horizontal word lines in the vertical direction, and a first dielectric layer disposed between the pillar gate electrode and the horizontal word lines in a cross section. The pillar gate electrode, the first dielectric layer, and the horizontal word lines correspond to memory cells including a plurality of variable capacitors spaced apart from each other in a vertical direction. The memory device further includes a selection transistor on the pillar gate electrode and the horizontal word lines and connected to one end of the pillar gate electrode, and a storage transistor under the pillar gate electrode and the horizontal word lines and connected to another end of the pillar gate electrode.

公开(公告)号：US20230328950A1

公开(公告)日：2023-10-12

申请号：US18175445

申请日：2023-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minjun LEE ,  Yongseok KIM ,  Hyuncheol KIM ,  Mintae RYU ,  Yongjin LEE

IPC: H10B12/00

CPC classification number: H10B12/00

Abstract: A semiconductor memory device includes a plurality of memory cells arranged on a substrate. Each of the plurality of memory cells may include a first transistor on the substrate and a second transistor on the first transistor. The first transistor may include a first channel region between a first source region and a first drain region, a first gate electrode, and a first gate insulating layer. The second transistor may include a pillar structure having a second drain region, a second channel region and a second source region sequentially stacked on the first gate electrode, a second gate electrode on one side of the second channel region, and a second gate insulating layer between the second channel region and the second gate electrode. The second drain region and the second source region may have a first conductivity type impurity region and a second conductivity type impurity region, respectively.

公开(公告)号：US20230206976A1

公开(公告)日：2023-06-29

申请号：US17875730

申请日：2022-07-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyunghwan LEE ,  Yongseok KIM ,  Hyuncheol KIM ,  Jongman PARK ,  Dongsoo WOO ,  Minjun LEE

IPC: G11C11/22 ,  H01L27/11597 ,  H01L21/28

CPC classification number: G11C11/223 ,  G11C11/2255 ,  G11C11/2257 ,  H01L27/11597 ,  H01L29/40111

Abstract: A semiconductor device including a substrate; a stack including electrodes and a channel separation pattern, the electrodes being stacked on the substrate and spaced apart from each other, and the channel separation pattern being between adjacent electrodes; and a vertical structure penetrating the stack, wherein the vertical structure includes a conductive pillar, a channel structure, and an interposing layer between the conductive pillar and the channel structure, the channel structure includes first and second channel layers vertically spaced apart from each other by the channel separation pattern, the electrodes include first and second electrodes, which are connected to the first and second channel layers, the channel separation pattern is between the first channel layer and the second channel layer, and the channel separation pattern is between one second electrode that is connected to the first channel layer and one first electrode that is connected to the second channel layer.

公开(公告)号：US20230140318A1

公开(公告)日：2023-05-04

申请号：US17875781

申请日：2022-07-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyuncheol KIM ,  Yongseok KIM ,  Dongsoo WOO ,  Kyunghwan LEE ,  Minjun LEE

IPC: H01L29/792 ,  H01L29/423 ,  G11C11/22 ,  G11C11/56

Abstract: A semiconductor memory device may include a substrate, first and second impurity regions on the substrate, first and second gate insulating layers sequentially stacked on the substrate and extended in a direction between the first and second impurity regions, and a gate electrode on the second gate insulating layer. The first and second impurity regions may have different conductivity types from each other, a bottom surface of the first gate insulating layer may be in direct contact with a top surface of the substrate, and the second gate insulating layer may include a ferroelectric material.

公开(公告)号：US20230096214A1

公开(公告)日：2023-03-30

申请号：US17952637

申请日：2022-09-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghwan LEE ,  Yongseok KIM ,  Hyuncheol KIM ,  Jongman PARK ,  Dongsoo WOO ,  Minjun LEE

IPC: H01L27/1159 ,  H01L27/11597

Abstract: A semiconductor device includes a plurality of gate electrodes extending on a substrate in a first horizontal direction and each including first and second vertical extension sidewalls that are opposite to each other, a channel arranged on the first vertical extension sidewall of each gate electrode and including a vertical extension portion, a ferroelectric layer and a gate insulating layer that are sequentially located between the channel layer and the first vertical extension sidewall of each gate electrode, an insulating layer on the second vertical extension sidewall of each gate electrode, and a plurality of bit lines electrically connected to the channel layer and extending in a second horizontal direction that is different from the first horizontal direction.