公开(公告)号：US12238920B2

公开(公告)日：2025-02-25

申请号：US17971256

申请日：2022-10-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihee Kim ,  Yeongshin Park ,  Hyunchul Yoon ,  Joonghee Kim ,  Jungheun Hwang

IPC: H10B12/00 ,  H01L21/764 ,  H01L21/768 ,  H01L29/66

Abstract: A semiconductor device includes bit line structures disposed on a substrate, each bit line structure comprising a bit line and an insulating spacer structure, buried contacts which fill lower portions of spaces between bit line structures in the substrate, and landing pads which fill upper portions of the spaces, extend from upper surfaces of the buried contacts to upper surfaces of the bit line structures, and are spaced apart from each other by insulating structures. A first insulating structure is disposed between a first landing pad and a first bit line structure. The first insulating structure includes a sidewall extending along a sidewall of the first landing pad toward the substrate. In a direction extending toward the substrate, the sidewall of the first insulating structure gets closer to a first sidewall of the first bit line structure.

公开(公告)号：US12237230B2

公开(公告)日：2025-02-25

申请号：US17238778

申请日：2021-04-23

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Bo-Yu Lai ,  Jyun-Chih Lin ,  Yen-Ting Chen ,  Wei-Yang Lee ,  Chia-Pin Lin ,  Wei Hao Lu ,  Li-Li Su

IPC: H01L21/8238 ,  H01L21/764 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A method of manufacturing a semiconductor device includes forming a fin structure over a substrate, forming a sacrificial gate structure over the fin structure, and etching a source/drain (S/D) region of the fin structure to form an S/D recess. The fin structure includes first semiconductor layers and second semiconductor layers alternately stacked. The method further includes depositing an insulating dielectric layer in the S/D recess, depositing an etch protection layer over a bottom portion of the insulating dielectric layer, and partially removing the insulating dielectric layer. The method further includes growing an epitaxial S/D feature in the S/D recess. The bottom portion of the insulating dielectric layer interposes the epitaxial S/D feature and the substrate.

公开(公告)号：US20250063744A1

公开(公告)日：2025-02-20

申请号：US18939603

申请日：2024-11-07

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsin-Li Cheng ,  Jyun-Ying Lin ,  Alexander Kalnitsky ,  Shih-Fen Huang ,  Shu-Hui Su ,  Ting-Chen Hsu ,  Tuo-Hsin Chien ,  Felix Ying-Kit Tsui ,  Shi-Min Wu ,  Yu-Chi Chang

IPC: H01L21/02 ,  H01L21/3213 ,  H01L21/764 ,  H01L23/00 ,  H01L29/66 ,  H01L29/94

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a substrate comprising first opposing sidewalls defining a first trench and second opposing sidewalls defining a second trench laterally offset from the first trench. A stack of layers comprises a plurality of conductive layers and a plurality of dielectric layers alternatingly stacked with the conductive layers. The stack of layers comprises a first segment in the first trench and a second segment in the second trench. A first lateral distance between the first segment and the second segment aligned with a first surface of the substrate is greater than a second lateral distance between the first segment and the second segment below the first surface of the substrate.

公开(公告)号：US12224212B2

公开(公告)日：2025-02-11

申请号：US18323907

申请日：2023-05-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yuan Chen ,  Huan-Chieh Su ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/764 ,  H01L23/528 ,  H01L27/088 ,  H01L29/417

Abstract: A semiconductor structure has a frontside and a backside. The semiconductor structure includes an isolation structure at the backside; one or more transistors at the frontside, wherein the one or more transistors have source/drain epitaxial features; two metal plugs through the isolation structure and contacting two of the source/drain electrodes from the backside; and a dielectric liner filling a space between the two metal plugs, wherein the dielectric liner partially or fully surrounds an air gap between the two metal plugs.

公开(公告)号：US12211886B1

公开(公告)日：2025-01-28

申请号：US18765489

申请日：2024-07-08

Applicant: GlobalFoundries U.S. Inc.

Inventor： Prateek Kumar Sharma ,  Venkata Narayana Rao Vanukuru ,  Kevin K. Dezfulian ,  Kenneth J. Giewont

IPC: H01L21/768 ,  H01L21/764 ,  H01L49/02

Abstract: Structures including an inductor and methods of forming such structures. The structure comprises a semiconductor substrate including a first plurality of sealed cavities and a back-end-of-line stack on the semiconductor substrate. Each sealed cavity includes an air gap, and the back-end-of-line stack includes an inductor having a winding that overlaps with the scaled cavities.

公开(公告)号：US12191193B2

公开(公告)日：2025-01-07

申请号：US17444775

申请日：2021-08-10

Applicant: Tokyo Electron Limited

Inventor： Tatsuya Yamaguchi

IPC: H01L21/764 ,  C23C16/44 ,  C23C16/455 ,  C23C16/48 ,  H01J37/32 ,  H01L21/02

Abstract: A method of manufacturing a semiconductor includes adjusting a temperature of a substrate having a recess formed therein and accommodated in a container to a temperature within a range of 200 degrees C. or higher and 280 degrees or lower, and laminating a polyurea film in the recess in the substrate by supplying isocyanate gas and amine gas into the container.

公开(公告)号：US12183622B2

公开(公告)日：2024-12-31

申请号：US17652338

申请日：2022-02-24

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Jingwen Lu

IPC: H01L21/764 ,  H01L21/762 ,  H10B12/00

Abstract: The present disclosure provides a method of manufacturing a semiconductor structure and a semiconductor structure. The method of manufacturing a semiconductor structure includes: providing a base, wherein the base includes an active region and a shallow trench isolation structure separating the active region, a word line trench is formed in the base, and the word line trench exposes a part of the active region and the shallow trench isolation structure; forming a first intermediate structure in the word line trenches, wherein the first intermediate structure covers side walls and a bottom wall of the word line trench, a first trench is formed in the first intermediate structure, the first intermediate structure includes a sacrificial structure, and the sacrificial structure includes a horizontal portion; and removing the horizontal portion of the sacrificial structure, and closing the first trench, and forming an air chamber.

公开(公告)号：US12176440B2

公开(公告)日：2024-12-24

申请号：US17518270

申请日：2021-11-03

Applicant: Winbond Electronics Corp.

Inventor： Shang-Rong Wu ,  Ming-Che Lin ,  Chung-Hsien Liu

IPC: H01L21/764 ,  H01L29/49 ,  H01L29/66 ,  H01L29/788

Abstract: A semiconductor structure and a method of forming the semiconductor structure are provided. The method of forming the semiconductor structure includes forming a floating gate layer on a substrate. A trench is formed in the floating gate layer and the substrate. A first dielectric layer is formed in the trench. A second dielectric layer is formed on the first dielectric layer. A third dielectric layer is formed on the second dielectric layer. A first sacrificial layer is formed on the third dielectric layer. A dielectric stack is formed on the first sacrificial layer. A control gate layer is formed on the dielectric stack. The first sacrificial layer is removed to form an air gap between the third dielectric layer and the dielectric stack.

公开(公告)号：US12176405B1

公开(公告)日：2024-12-24

申请号：US18664386

申请日：2024-05-15

Applicant: GlobalFoundries Singapore Pte. Ltd.

Inventor： Khee Yong Lim ,  Xinfu Liu ,  Xiao Mei Elaine Low

IPC: H01L29/417 ,  H01L21/764 ,  H01L29/423 ,  H01L29/66

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. The structure comprises a semiconductor layer, a first raised source/drain region on the semiconductor layer, a second raised source/drain region on the semiconductor layer, a gate electrode laterally between the first raised source/drain region and the second raised source/drain region, a first airgap laterally between the first raised source/drain region and the gate electrode, and a second airgap laterally between the second raised source/drain region and the gate electrode. The gate electrode includes a first section and a second section between the first section and the semiconductor layer, the first section of the gate electrode has a first width, the second section of the gate electrode has a second width, and the first width is greater than the second width.

公开(公告)号：US20240395605A1

公开(公告)日：2024-11-28

申请号：US18789716

申请日：2024-07-31

Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Janbo Zhang ,  Chao-Wei Lin ,  Chia-Yi Chu ,  Yu-Cheng Tung ,  Ken-Li Chen ,  Tsung-Wen Chen

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/764 ,  H01L23/532 ,  H10B12/00

Abstract: A method of manufacturing a semiconductor memory device, including steps of providing a substrate, forming word lines extending in a first direction in the substrate, forming bit lines extending in a second direction over the word lines, forming partition structures between the bit lines and right above the word lines, forming storage node contacts in spaces defined by the bit lines and the partition structures, wherein a portion of each of the storage node contacts protruding from top surfaces of the bit lines and the partition structures is contact pad, forming a first dielectric layer on the contact pads, the bit lines and the partition structures, forming a second dielectric layer on the first dielectric layer, and performing an etch back process to remove parts of the second dielectric layer, so that only parts of the second dielectric layer on sidewalls of the contact pads remain.